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atv hp edt datasheet hardware description rev. 3.1, 2015-07-30 1EDI2002AS single channel isolat ed driver for in verter systems ad step eicedriver ? sil high voltage igbt driver fo r automotive applications
edition 2015-07-30 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
eicedriver ? sil 1EDI2002AS datasheet 3 rev. 3.1, 2015-07-30 hardware description trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econ odual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, or iga?, primarion?, prim epack?, primestack?, pro-sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smartlewis?, solid flash?, tempfe t?, thinq!?, trench stop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, revision history page or item subjects (major changes since previous revision) rev 2.2, 2014-07-25 page 29 added note: ?the contents of a frame...? page 29 added note: ?in case of permanent...? page 44 added note: ?the pulse suppressor...? page 51 corrected table 2-14 page 54 updated chapter 2.4.10.1.17 page 55 updated chapter 2.4.10.1.19 . page 83 update pid value. page 86 updated reset value of register pstat2 . page 102 update sid value. page 103 correct sstat definition of bits 15 and 14 to rh. page 117 updated definition of bit field dsatbt . page 118 updated definition of bit field ocpbt . page 127 updated table 5-1 page 129 updated figure 5-1 page 130 corrected table 5-2 page 131 updated footnote 2) in table 5-3 . page 131 updated value r thjcbot in table 5-4 page 132 updated parameters v uvlo2 and v ovlo2 in table 5-5 . page 133 updated parameter f clk1 in table 5-6 page 134 updated parameters r pdin1 and i inpr1 in table 5-7 page 136 updated parameters r pdin2 and r pdio2 and updated parameter r pdosd2 in table 5-13 page 138 updated parameters v gpon0 , v gpon1 v gpon2 , t pdisto , v gpof15 in table 5-17 page 140 updated parameters r pudesat2 , v desat0 , v desat1 , v desat2 in table 5-18 page 140 updated parameter r puocp2 in table 5-19 page 143 updated parameter t dead , t offdesat2 in table 5-23 page 144 updated parameter t fsclk , removed parameter t sclkp table 5-24
eicedriver ? sil 1EDI2002AS datasheet 4 rev. 3.1, 2015-07-30 hardware description firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-02-24
eicedriver ? sil 1EDI2002AS table of contents datasheet 5 rev. 3.1, 2015-07-30 hardware description table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 product definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2.1 primary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2.2 secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2.3 pull devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.2 clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.3 pwm input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.4 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.4.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.4.3 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.4.4 spi data integrity support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.4.4.1 parity bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.4.4.2 spi error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.4.5 protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.4.5.1 command catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.4.5.2 word convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.4.5.3 enter_cmode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.4.5.4 enter_vmode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.4.5.5 exit_cmode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.4.5.6 nop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.4.5.7 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.4.5.8 writeh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.4.5.9 writel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.5.1 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.5.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5.2.1 events and state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5.2.2 emergency turn-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.5.2.3 ready, disabled, enabled and active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.5.3 operation modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.5.4 activating the device after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.5.5 activating the device after an event class a or b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.5.6 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table of contents
eicedriver ? sil 1EDI2002AS table of contents datasheet 6 rev. 3.1, 2015-07-30 hardware description 2.4.6 driver functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.6.2 switching sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.4.6.3 disabling the output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.6.4 passive clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.7 fault notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.8 en signal pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.9 reset events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.10 operation in configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.10.1 static configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.10.1.1 configuration of the spi parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.10.1.2 configuration of nflta activation in case of tristate event . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.10.1.3 configuration of the stp minimum dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 2.4.10.1.4 configuration of the en/fen mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.5 configuration of the digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.6 configuration of dout signal activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.7 configuration of the v be compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.8 deactivation of output stage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.9 deactivation of events class a due to pin osd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.10 clampin g of desat pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.10.1.11 activation of the pulse suppresso r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.12 configuration of the verificati on mode time out duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.13 desat threshold level configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.14 configuration of the tton delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.15 configuration of daclp activation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.16 ovlo3 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.17 configuration of the ttoff delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.10.1.18 configuration of the safe ttoff plateau level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.10.1.19 configura tion of the desat blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.10.1.20 configuration of the ocp blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.10.1.21 configuration of daclp activation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.10.2 dynamic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.10.3 delay calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4.11 low latency digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3 protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1 supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2 protection functions: category a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2.1 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2.2 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.3 external enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.4 output stage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3 protection functions: category b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.1 power supply voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.2 internal supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3.2.1 lifesign watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3.2.2 oscillator monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3.2.3 memory supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.4 protection functions: category c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.4.1 shoot through protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.4.2 gate monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4.3 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
eicedriver ? sil 1EDI2002AS table of contents datasheet 7 rev. 3.1, 2015-07-30 hardware description 3.4.4 spi error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.5 active short circuit support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.4.6 igbt state monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5 protection functions: category d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.1 operation in verification mode and weak active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.2 weak turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.3 desat supervision level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.4 desat supervision level 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.5 desat supervision level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.6 ocp supervision level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.7 ocp supervision level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.8 power supply monitoring supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.9 internal clock supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.5.10 dio supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.1 primary register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2 secondary registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.3 read / write address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.5.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.5.2 internal oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.5.3 primary i/o electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.5.4 secondary i/o electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.5.5 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.5.6 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.5.7 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.5.8 low latency digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.5.9 dout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.5.10 over temperature warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.5.11 error detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.5.12 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.5.13 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
eicedriver ? sil 1EDI2002AS list of figures datasheet 8 rev. 3.1, 2015-07-30 hardware description figure 2-1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2-2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 2-3 pwm input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2-4 stp: inhibition time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2-5 stp: example of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2-6 spi regular bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 2-7 spi daisy chain bus topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 2-8 response answer principle - daisy chain topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 2-9 response answer principle - regular topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 2-10 spi commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 2-11 operating modes state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 2-12 output stage diagram of principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 2-13 ttoff: principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 2-14 tton: principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 2-15 ttoff: pulse suppressor aborting a turn-on sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 2-16 idealized switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 2-17 output stage disable: principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 2-18 low latency digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 3-1 desat function: diagram of principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 3-2 desat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3-3 desat operation with desat clamping enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 figure 3-4 ocp function: principle of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 3-5 power supply supervision function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 3-6 shoot through protection: principl e of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 3-7 gate monitoring function: timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 3-8 asc strategy support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 3-9 idealized weak turn-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 5-1 typical application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 5-2 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 6-1 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 6-2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 list of figures
eicedriver ? sil 1EDI2002AS list of tables datasheet 9 rev. 3.1, 2015-07-30 hardware description table 2-1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2-2 internal pull devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2-3 spi command catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 2-4 word convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 2-5 enter_cmode request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 2-6 enter_vmode request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 2-7 exit_cmode request and answer messag es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 2-8 nop request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 2-9 read request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 2-10 writeh request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 2-11 writel request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 2-12 failure notification clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 2-13 reset events summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 2-14 pin behavior (primary side) in case of reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 2-15 pin behavior (secondary side) in case of reset condit ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 3-1 safety related functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 3-2 desat protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 3-3 ocp function overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 3-4 external enable function overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 3-5 output stage monitoring overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 3-6 power supply voltage monitoring overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 3-7 system supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 3-8 stp overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 3-9 gate monitoring overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 3-10 temperature monitoring overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 3-11 spi error detection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 3-12 active short circuit support overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 3-13 igbt state monitoring overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 3-14 desat supervision level 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 3-15 desat supervision level 2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 3-16 desat supervision level 3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 3-17 ocp supervision level 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 3-18 ocp supervision level 3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 3-19 power supply monitoring supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 3-20 primary clock supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 3-21 dio supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 4-1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 4-2 bit access terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 4-3 read access validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 4-4 write access validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 5-1 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 5-2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 5-3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 5-4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 5-5 power supplies characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 5-6 internal oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 5-7 electrical characteristics for pins: inp , instp , en/fen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 5-8 electrical characteristics for pins: nrst/rdy , sclk , sdi , ncs , dio1 (input) . . . . . . . . . . . . . 134 table 5-9 electrical characteristics for pins: sdo , dout , dio1 (output) . . . . . . . . . . . . . . . . . . . . . . . . . 135 list of tables
eicedriver ? sil 1EDI2002AS list of tables datasheet 10 rev. 3.1, 2015-07-30 hardware description table 5-10 electrical characteristics for pins: nflta , nfltb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 5-11 electrical characteristics for pins: gate , desat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 5-12 electrical characteristics for pins: ton , toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 5-13 electrical characteristics for pins: osd , debug , dio2 (input) . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 5-14 electrical char acteristics for pin: nuv2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 5-15 electrical characteristics for pins: daclp , dio2 (output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 5-16 electrical char acteristics for pin: vreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 5-17 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 5-18 desat characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 5-19 ocp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 5-20 digital channel characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 5-21 data out characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 5-22 over temperature warning characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 5-23 error detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 5-24 spi interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 5-25 isolation characteristics refe rring to din en 60747-5-2 (vde 0884 - 2):2003-01 . . . . . . . . . . . . 145 table 5-26 isolation characteristics referring to ul 1577. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
product name ordering code package 1EDI2002AS sp001362894 pg-dso-36 1EDI2002AS datasheet 11 rev. 3.1, 2015-07-30 hardware description 1 product definition 1.1 overview the 1EDI2002AS is a high-voltage igbt gate driver designed for automotive motor drives above 5 kw. the 1EDI2002AS is based on infineon?s coreless transformer (clt) technology, providing galvanic insulation between low voltage and hi gh voltage domains. the device has been designed to support 400 v, 600 v and 1200 v igbt technologies. the 1EDI2002AS can be connected on the low voltage side (?primary? side) to 5 v logic. a standard spi inte rface allows the logic to configure and to control the advanced functions implemented in the driver. on the high voltage side (?secondary? side), the 1edi20 02as is dimensioned to drive an external booster stage. short propagation delays and controlled internal tolera nces lead to minimal distortion of the pwm signal. a large panel of safety-related functions has been implem ented in the 1EDI2002AS, in order to support functional safety requirements at system level (as per iso 26262). besides, thos e integrated features ease the implementation of active short circuit (asc) strategies. the 1EDI2002AS can be used optimally with infineon?s 1ebn100 xae ?eicedriver? boos t? booster stage family. 1.2 feature overview the following features are supported by the 1EDI2002AS: functional features ? single channel igbt driver. ? on-chip galvanic insulation (up to 6kv). ? support of 600 v and 1200 v igbt technologies. ? low propagation delay and minimal pwm distortion. ? support of 5 v logic levels (primary side). ? 16-bit standard spi interface (up to 2 mbaud) with daisy chain support (primary side). ? enable input pin (primary side). ? pseudo-differential inputs for critical signals (primary side). ? power-on reset pin (primary side). ? debug mode. ? pulse suppressor.
eicedriver ? sil 1EDI2002AS product definition datasheet 12 rev. 3.1, 2015-07-30 hardware description ? fully programmable active clampi ng inhibit signal (secondary side). ? fully programmable two-level turn on (tton). ? low latency digital channel. ? optimal support of eiceboost functions. ? 36-pin pg-dso-36 green package. ? automotive qualified (as per aec q100). safety relevant features ? programmable desaturation monitoring. ? overcurrent protection. ? fully programmable two-level turn-off. ? automatic emergency turn-off in failure case. ? automatic or externally triggered disa bling of the output stage (tristate). ? under- and over-voltage supervision of all the power supplies (both primary and secondary sides). ? nflta and nfltb notification pins for fast system response time (primary side). ? safe internal state machine. ? weak turn-on functionality. ? internal overtemperature sensor (secondary side). ? internal clock monitoring. ? gate signal monitoring. ? igbt state monitoring. ? individual error and status flags readable via spi. ? support for active short circuit strategies. ? full diagnosticability. ? in-application testability of safety critical functions. ? suitable for systems up to asil d requirements (as per iso 26262). 1.3 target applications ? inverters for automotive hybrid electric vehicles (hev) and electric vehicles (ev). ? high voltage dc/dc converter. ? industrial drive.
eicedriver ? sil 1EDI2002AS functional description datasheet 13 rev. 3.1, 2015-07-30 hardware description 2 functional description 2.1 introduction the 1EDI2002AS is an advanced single channel igbt driv er that can also be used for driving power mos devices. the device has been developed in order to optimize the design of high performance safety relevant automotive systems. the device is based on infineon?s co reless transformer technology and c onsist of two chips separated by a galvanic isolation. the low voltage (p rimary) side can be connected to a standard 5 v logic. the high voltage (secondary) side is in the dc-link voltage domain. internally, the data transfers are ensured by two independent communication channels. one channel is dedicated to transferring the on and off information of the pwm in put signal only. this channel is unidirectional (from primary to secondary). because this channel is ded icated to the pwm information, latency time and pwm distortion are minimized. the second channel is bidirectiona l and is used for all the other data transfers (e.g. status information, etc). the 1EDI2002AS supports advanced functions in orde r to optimize the switch ing behavior of the igbt. furthermore, it supports several monitoring and protection functions, making it suitable for systems having to fulfill asil requirements (as per iso 26262).
eicedriver ? sil 1EDI2002AS functional description datasheet 14 rev. 3.1, 2015-07-30 hardware description 2.2 pin configuration and functionality 2.2.1 pin configuration figure 2-1 pin configuration table 2-1 pin configuration pin number symbol i/o voltage class function 1,9,18 vee2 supply supply negative power supply 1) . 2 ton output 15v secondary turn-on output. 3 vcc2 supply supply positive power supply. 4 toff output 15v secondary turn-off output. 5 desat input 15v secondary des aturation prot ection input. 6 gate input 15v secondary gate monitoring input. 7 gnd2 ground ground ground. 8 iref2 input 5v secondary external reference input. 10 vreg output 5v secondary reference output voltage. 11 ocp input 5v secondary over current protection. 12 ocpg ground ground ground for the ocp function, 13 debug input 5v secondary debug input. ocpg vreg desat iref2 gnd2 toff vee2 nuv2 gate debug dio2 vee2 osd vcc2 daclp ocp ton vee2 gnd1 instp en/fen nrst /rdy dio1 sclk nflta ncs ref 0 inp iref1 vcc1 gnd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 25 24 23 22 21 20 19 nfltb 26 sdi 27 gnd1 28 sdo 29 dout
eicedriver ? sil 1EDI2002AS functional description datasheet 15 rev. 3.1, 2015-07-30 hardware description 14 daclp output 5v secondary active clamping disable output. 15 osd input 5v secondary output stage disable input. 16 dio2 input / output 5v secondary digital i/o. 17 nuv2 output 5v secondary v cc2 not valid notification output. 19, 28, 36 gnd1 ground ground ground 2) . 20 dio1 input / output 5v primary digital i/o. 21 sclk input 5v primary spi serial clock input. 22 sdi input 5v primary spi serial data input. 23 ncs input 5v primary spi chip select input (low active). 24 sdo output 5v primary spi serial data output. 25 dout output 5v primary desat comparator output. 26 nfltb output 5v primary fault b output (low active, open drain). 27 nflta output 5v primary fault a output (low active, open drain). 29 nrst/rdy input/output 5v primary reset input (low active, open drain). this signal notifies that the device is ?ready?. 30 en/fen input 5v primary enable input. 31 ref0 ref. ground ground reference ground for signals inp , instp , en/fen . 32 inp input 5v primary positive pwm input. 33 instp input 5v primary monitoring pwm input. 34 vcc1 supply input supply positive power supply. 35 iref1 input 5v primary external reference input. 1) all vee2 pins must be connected together. 2) all gnd1 pins must be connected together. table 2-1 pin configuration (cont?d) pin number symbol i/o voltage class function
eicedriver ? sil 1EDI2002AS functional description datasheet 16 rev. 3.1, 2015-07-30 hardware description 2.2.2 pin functionality 2.2.2.1 primary side gnd1 ground connection for the primary side. vcc1 5v power supply for the primary side (referring to gnd1). inp non-inverting pwm input of the driver. the internal struct ure of the pad makes the ic robust against glitches. an internal weak pull-down resistor to v ref0 drives this input to low state in case the pin is floating. instp monitoring pwm input for shoot through protection. the inte rnal structure of the pad ma kes the ic robust against glitches. an internal weak pull-down resistor to v ref0 drives this input to low state in case the pin is floating. ref0 reference ground signal for the signals inp , instp , en/fen . this pin should be connected to the ground signal of the logic issuing those signals. en/fen enable input signal. this signal allows the logic on th e primary side to turn-off and deactivate the device. an internal weak pull-down resistor to v ref0 drives this input to low state in case the pin is floating. this pin reacts on logic levelsor on a periodic signal , depending on the device?s configuration. nflta open-drain output signal used to report major failure events (event class a). in case of an error event, nflta is driven to low state. this pin shall be connected externally to v cc1 with a pull-up resistance. nfltb open-drain output signal used to report major failure events (event class b). in case of an error event, nfltb is driven to low state. this pin shall be connected externally to v cc1 with a pull-up resistance. sclk serial clock input for the spi interface. an internal weak pull-up device to v cc1 drives this input to high state in case the pin is floating. sdo serial data output (push-pull) or the spi interface. sdi serial data input for the spi interface. an internal weak pull-up device to v cc1 drives this input to high state in case the pin is floating.
eicedriver ? sil 1EDI2002AS functional description datasheet 17 rev. 3.1, 2015-07-30 hardware description ncs chip select input for the spi interface. this signal is low active. an internal weak pull-up device to v cc1 drives this input to high state in case the pin is floating. iref1 reference input of the primary chip. this pin shall be connected to v gnd1 via an external resistor. nrst/rdy open drain reset input. this signal is low-active. when a va lid signal is received on this pin, the device is brought in its default state. this signal is al so used as a ?ready notification?. a high level on this pin indicates that the primary chip is functional. dout enhanced desat functionalit y comparator status outpu t. this signal allows real-t ime monitoring of the igbt state. dio1 i/o for the digital channel. depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). an internal weak pull-down resistor to v gnd1 drives this input to low state in case the pin is floating. 2.2.2.2 secondary side vee2 negative power supply for the secondary side, referring to v gnd2 . vcc2 positive power supply for the secondary side, referring to v gnd2 . gnd2 reference ground for the secondary side. desat desaturation protection input pin. the functi on associated with this pin monitors the v ce voltage of the igbt. the detection threshold is programmable. an internal pull-up resistor to v cc2 drives this signal to high level in case it is floating. ocp over current protection input pin. th e function associated with this pin monitors the voltage across a sensing resistance located on the auxilia ry path of a current sense igbt. an internal weak pull- up resistor to the internal 5v reference drives this input to high state in case the pin is floating. ocpg over current protection ground.
eicedriver ? sil 1EDI2002AS functional description datasheet 18 rev. 3.1, 2015-07-30 hardware description ton output pin for turning on the igbt. toff output pin for turning off the igbt. gate input pin used to monitor the igbt gate voltage. osd output stage disable input. a high level on this pin tristate s the output stage. an inte rnal weak pull-down resistor to v gnd2 drives this input to low state in case the pin is floating. daclp output pin used to disable the active clamping function of the booster. debug debug input pin. this pin is latched at power-up. when a high level is detected on this pin, the device enters a special mode where it can be operated without spi interface. this feature is for development purpose only. this pin should normally be tied to v gnd2 . an internal weak pull-down resistor to v gnd2 drives this input to low state in case the pin is floating. iref2 reference input of the secondary chip. this pin shall be connected to v gnd2 via an external resistor. vreg reference output voltage. this pin shall be connected to an external capacitance to v gnd2 . nuv2 v cc2 not valid notification signal (open drain). this signal drives a low level when v cc2 is not valid or when the internal 5v digital supply is not valid . when both supplies are valid, this pin is in high impedance state. this pin shall be connected externally to a 5v reference with a pull-up resistance. dio2 i/o for the digital channel. depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). an internal weak pull-down resistor to v gnd2 drives this input to low state in case the pin is floating. 2.2.2.3 pull devices some of the pins are connected internally to pull- up or pull-down devices. this is summarized in table 2-2 . table 2-2 internal pull devices signal device inp weak pull down to v ref0 instp weak pull down to v ref0
eicedriver ? sil 1EDI2002AS functional description datasheet 19 rev. 3.1, 2015-07-30 hardware description en/fen weak pull down to v ref0 sclk weak pull up to v cc1 sdi weak pull up to v cc1 ncs weak pull up to v cc1 dio1 weak pull down to v gnd1 desat weak pull up to v cc2 dio2 weak pull down to v gnd2 osd weak pull down to v gnd2 ocp weak pull up to 5v internal reference debug weak pull down to v gnd2 table 2-2 internal pull devices signal device
eicedriver ? sil 1EDI2002AS functional description datasheet 20 rev. 3.1, 2015-07-30 hardware description 2.3 block diagram figure 2-2 block diagram primary logic secon- dary logic vee2 desat daclp output stage - switching control osd vcc2 desat ton ocp gnd1 vcc1 p-supply nflta inp instp en/fen ncs sdi sdo sclk t sensor gate toff nfltb ocp pwm input stage spi interface ref0 osc 1 iref1 osc2 iref2 gnd2 p-supply start-stop osc wdg wdg dout nrst/rdy vreg debug dio1 dio2 ocpg nuv2
eicedriver ? sil 1EDI2002AS functional description datasheet 21 rev. 3.1, 2015-07-30 hardware description 2.4 functional block description 2.4.1 power supplies on the primary side, the 1EDI2002AS needs a single 5 vsupply source v cc1 for proper operation. this makes the device compatible to most of the microcon trollers available for automotive applications. on the secondary side, the 1EDI2002AS needs two power supplies for proper operation. ? the positive power supply v cc2 is typically set to 15 v (referring to v gnd2 ). ? the negative supply v ee2 is typically set to -8 v (referring to v gnd2 ). under- and over-voltage monitoring is performed continuously during operation of the device (see chapter 3.3.1 ). a 5v supply for the digital domain on the second ary side is generated internally (present at pin vreg ). 2.4.2 clock domains the clock system of the 1EDI2002AS is based on three oscillators defining each a clock domain: ? one rc oscillator (osc1) for the primary chip. ? one rc oscillator (osc2) for the seco ndary chip exceptin g the output stage. ? one start-stop oscillator (ssosc2) for the output st age on the secondary side. the two rc oscillators are runn ing constantly. they are also monitored co nstantly, and large deviations from the nominal frequency are identified as a system failure (event class b, see chapter 3.3.2.2 ). the start stop oscillator is controlled by the pwm command.
eicedriver ? sil 1EDI2002AS functional description datasheet 22 rev. 3.1, 2015-07-30 hardware description 2.4.3 pwm input stage the pwm input stage generates from the external signals inp , instp and en/fen the turn-on and turn-off commands to the secondary side. the general structure of the pwm input block is shown figure 2-3 . figure 2-3 pwm input stage signals inp , instp and en/fen are pseudo-differential, in the sense that they are not referenced to the common ground gnd1 but to signal ref0 . this is intended to make the device more robust against ground bouncing effects. note: glitches shorter than t inpr1 occurring at signal inp are filtered internally. note: pulses at inp below t inppd might be distorted or suppressed. the 1EDI2002AS supports non-inverted pwm signals only. when a high level on pin inp is detected while signals instp and en/fen are valid, a turn-on command is issued to the secondary chip. a low level at pin inp issues a turn-off command to the secondary chip. signal en/fen can inhibit turn-on commands received at pin inp . a valid signal en/fen is required in order to have turn-on commands issued to the secondary chip. if an invalid signal is provided , the pwm input stage issues constantly turn-off command s to the secondary chip. the functionality of signal en/fen is detailed in chapter 2.4.8 . note: after an invalid-to va lid-transition of signal en/fen , a minimum delay of t inpen should be inserted before turning inp on. as shown in figure 2-4 , signal instp provides a shoot-through protection (stp) to the system. when signal at pin instp is at high level, the internal signal inhibit_act is activated. the inhibition time is defined as the pulse duration of signal inhibit_act. it corresponds to the pulse duration of signal instp to which a minimum dead time is added. during the inhibition time, rising edges of signal inp are inhibited. bit pstat2 . stp is set for the duration of the inhibition time. the deadtime is programmable with bit field pcfg2 . stpdel . ref0 lo gic vcc1 inp instp en pwm_cmd validity check en_valid inhibit time generation inhibit_act.
eicedriver ? sil 1EDI2002AS functional description datasheet 23 rev. 3.1, 2015-07-30 hardware description figure 2-4 stp: inhibition time definition it shall be noted that during the inhibition time, signal pwm_cmd is not forced to low. it means that if the device is already turned-on when instp is high, it stays turned-on until the signal at pin inp goes low. this is depicted in figure 2-5 . figure 2-5 stp: example of operation when a condition occurs where a rising edge of signal inp is inhibited, an error no tification is issued. see chapter 3.4.1 for more details. instp inp inhibit_act pwm_cmd dead time inhibition time instp inp inhibit_act pwm_cmd inhibition time dead time inhibited edge
eicedriver ? sil 1EDI2002AS functional description datasheet 24 rev. 3.1, 2015-07-30 hardware description 2.4.4 spi interface this chapter describes the f unctionality of the spi block. 2.4.4.1 overview the standard spi interface implemented on the 1edi2002 as is compatible with most of the microcontrollers available for automotive and industria l applications. the following features are supported by the spi interface: ? full-duplex bidirectional communication link. ? spi slave mode (only). ? 16-bit frame format. ? daisy chain capability. ? msb first. ? parity check (optional) and parity bit generation (lsb). the spi interface of the 1EDI2002AS provides a standardi zed bidirectional communication interface to the main microcontroller. from the arch itectural point of view, it fu lfills the following functions: ? initialization of the device. ? configuration of the device (static and runtime). ? reading of the status of the device (static and runtime). ? operation of the verification modes of the device. the purpose of the spi interface is to exchange data which have relaxed timing constraints compared to the pwm signals (from the point of view of the motor control algorithm). the igbt switching behavior is for example controlled directly by the pwm input. similarly, critical app lication failures requiring fast reaction are notified on the primary side via the feedback signals nflta , nfltb and nrst/rdy . in order to minimize the complexity of the end-applic ation and to optimize the microcontroller?s resources, the implemented interface has da isy chain capability. several (typically 6) 1EDI2002AS devices can be combined into a single spi bus.
eicedriver ? sil 1EDI2002AS functional description datasheet 25 rev. 3.1, 2015-07-30 hardware description 2.4.4.2 general operation the spi interface of the 1EDI2002AS supports full duplex operation. the interface relies on four communication signals: ? ncs : (not) chip select. ? sclk : serial clock. ? sdi : serial data in. ? sdo : serial data out. the spi interface of the 1EDI2002AS supports slave operation only. an spi ma ster (typically, the main microcontroller) is connected to one or several 1edi20 02as devices, forming an spi bus. several bus topologies are supported. a regular spi bus topology can be used where each of the slaves is controlled by an individual chip select signal ( figure 2-6 ). in this case, the number of slaves on the bu s is only limited by the application?s constraints. figure 2-6 spi regular bus topology in order to simplify the layout of the pcb and to reduce the number of pins used on the microcontroller?s side, a daisy chain topology can also be used. the chain?s de pth is not limited by the 1EDI2002AS itself. a possible topology is shown figure 2-7 . sclk master sdo sdi ncs1 sclk sdi sdo ncs slave 1 sclk sdi sdo ncs slave 2 sclk sdi sdo ncs slave n ... ... ... ncsn ... ... ncs2
eicedriver ? sil 1EDI2002AS functional description datasheet 26 rev. 3.1, 2015-07-30 hardware description figure 2-7 spi daisy chain bus topology physical layer the spi interface relies on two shift registers: ? a shift output register, reacting on the rising edges of sclk . ? a shift input register, reac ting on the falling edges of sclk . when signal ncs is inactive, the signals at pins sc lk and sdi are ignored. the output sdo is in tristate. when ncs is activated, the shift output r egister is updated internally with th e value requested by the previous spi access. at each rising edge of the sclk signal (while ncs is active), the shift output register is serially shifted out by one bit on the sdo pin (msb first). at each falling edge of the cl ock pulse, the data bit available at the input sdi is latched and serially shifted into the shift input register. at the deactivation of ncs , the spi logic checks how many rising and falling edges of the sclk signal have been received. in case both counts differ and / or are not a multiple of 16, an spi error is generated. the spi block then checks the validity of the received 16-bit word. in case of a non valid data, an spi error is generated. in case no error is detected, the data is decoded by the internal logic. the ncs signal is active low. input debouncing filters the input stages of signals sdi , sclk , and ncs include each a debouncing filter. the input signals are that way filtered from glitches and noise. the input signals sdi and sclk are analyzed at each edge of the internal clock derived from osc1. if the same external signal value is sampled three times consecutively, the signal is considered as valid and is processed by the spi logic. otherwise, the transition is considered as a glitch and is discarded. sclk master sdo sdi ncs sclk sdi sdo ncs slave 1 sclk sdi sdo ncs slave 2 sclk sdi sdo ncs slave n ... ... ... ...
eicedriver ? sil 1EDI2002AS functional description datasheet 27 rev. 3.1, 2015-07-30 hardware description the input signal ncs is sampled at a rate corresponding to the peri od of the internal clock derived from osc1. if the same external signal value is sampled two times c onsecutively, the signal is considered as valid and is processed by the spi logic. other wise, the transition is considered as a glitch and is discarded. 2.4.4.3 definitions command a command is a high-level command issued by the spi master which aims at generating a specific reaction in the addressed slave. the command is physically translated into a request message by the spi master. the correct reception of the request message by t he spi slave leads to a specific action inside the slave and to the emission of an answer message by the slave. example: the read command leads to the transfer of the va lue of the specified register from the device to the spi master. word a word is a 16-bit sequence of shifted data bits. transfer a transfer is defined as the spi data transfers (in both directions ) occurring betwee n a falling edge of ncs and the next consecutiv e rising edge of ncs . request message a request message is a word issued by the spi master a nd addressing a single slave. a request message relates to a specific command. answer message an answer message is a well-defined word issued by a single spi slave as a response to a request message. transmit frame a transmit frame is a sequence of one or several words s ent by the spi master within one spi transfer. in regular spi topologies, a transmit frame is in practice identical to a data word. in daisy chain topologies, a transmit frame is a sequence of data words belonging to different request messages. receive frame a receive frame is a sequence of one or several word s received by the spi master within one spi transfer. in regular spi topologies, a receive frame is in practice ident ical to a data word. in daisy chain topologies, a receive frame is a sequence of data words belonging to different answer messages. the spi protocol supported by the 1e di2002as is based on the request / answer principle. the master sends a defined request message to which the slave answers with the corresponding answer message ( figure 2-8 , figure 2-9 ). due to the nature of the spi interface, the answer message is shifted, compared to the request message, by one spi transfer. it means, for example, that the last word of answer message n is transmitted by the slave while the master sends the first word of request message n+1.
eicedriver ? sil 1EDI2002AS functional description datasheet 28 rev. 3.1, 2015-07-30 hardware description figure 2-8 response answer principle - daisy chain topology figure 2-9 response answer principle - regular topology the first word transmitted by the device af ter power-up is the content of register pstat . chip select ncs master serial output (seen at sdi) ... rm1 ... rm2 ... am1 ... ... ... ... transfer transmit frame receive frame master serial input (seen at sdo) ... rmn wn ... ... am2 ... ... ... ... ... ... ... ... amn word i answer message of slave i ... ... inactive active request message for slave i ... chip select ncs for slave i master serial output (seen at sdi) rm1 am1 ... transfer transmit frame receive frame master serial input (seen at sdo) ... am2 ... ... amn inactive active rm2 rmn word ... answer meassage request message
eicedriver ? sil 1EDI2002AS functional description datasheet 29 rev. 3.1, 2015-07-30 hardware description 2.4.4.4 spi data integrity support 2.4.4.4.1 parity bit by default, the spi link relies on an odd parity protection scheme for each transmitted or received 16-bit word of the spi message. the parity bit corresponds to the lsb of the 16-bit word. therefore, the effective payload of a 16-bit word is 15 data bit (plus one parity bit). the pa rity bit check (on the receiv ed data) can be disabled by clearing bit pcfg . paren . in this case, the parity bit is considered as ?don?t care?. the generation of the parity bit by the driver for transmitted words can not be disabled (but can be considered as ?don ?t care? by the spi master). note: for fixed value commands (enter_cmode, enter_ vmode, exit_cmode, nop), it has to be ensured that the value of the parity bit is correct even if parity check is disabled. otherwise, an spi error will be generated. 2.4.4.4.2 spi error when the device is not able to process an incoming re quest message, an spi error is generated: the received message is discarded by the driver, bit per . spier is set and the erroneous message is answered with an error notification (bit lmi set). several failures generate an spi error: ? a parity error is detected on the received word. ? an invalid data word format is received (e.g. not a 16 bit word). ? a word is received, which does not corresponding to a valid request message. ? a command is received which can not be processed. for example, the driver receives in active mode a command which is only valid in other operating modes. another typical example is a read access to the secondary while the previous read access is not yet completed (device ?busy?). ? an spi access to an invalid address. note: the content of a frame with lmi bit set is the value of register pstat . note: in case of permanent lmi error induced by system failures, it is recommended to apply a reset via pin nrst/rdy .
eicedriver ? sil 1EDI2002AS functional description datasheet 30 rev. 3.1, 2015-07-30 hardware description 2.4.4.5 protocol description 2.4.4.5.1 command catalog table 2-3 gives an overview of the command catalog suppo rted by the device. the full description of the commands and of the corresponding request and answer messages is provided in the following sections. an overview of the commands is given figure 2-10 . figure 2-10 spi commands overview 2.4.4.5.2 word convention in order to simplify the description of the spi commands, the following conventions are used ( table 2-4 ). table 2-3 spi command catalog acronym short description valid in mode enter_cmode enters into configuration mode. opm0, opm1 enter_vmode enters into verification mode. opm2 exit_cmode leaves configuration mode to enter into configured mode. opm2 read reads the register value at the specified address. all nop triggers no action in the device (equivalent to a ?nop?). all writeh update the most significant byte of the internal write buffer. all writel updates the least significant byte of the internal write buffer, and copies the contents of the complete buffer into the addressed register. the write buffer is cleared afterwards. all (with restrictions) table 2-4 word convention acronym value va(register) value of register register p b parity bit m e ssa g e p enter_cmode 000 11 000 1 0000000 enter_vmode 000 1 000 1 0 1 000000 exit_cmode 000 1 00 1 000 1 00000 nop 000 1 0 1 00000 1 0000 read 0000 a4 a3 a2 a1 a0 0 1 0 1 0 1 x writeh 0 1 000 1 0 d15 d14 d13 d12 d11 d10 d9 d8 x writel 1 0 1 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 x data command
eicedriver ? sil 1EDI2002AS functional description datasheet 31 rev. 3.1, 2015-07-30 hardware description 2.4.4.5.3 enter_cmode command the goal of this function is to set the device into c onfiguration mode. after reception of a valid enter_cmode command, mode opm2 is active. this command is only valid in default mode (opm0 and opm1). in case the request message is received while opm1 is not active , the complete command is discarded and an spi error occurs. table 2-5 describes the request message and the corresponding answer message. 2.4.4.5.4 enter_vmode command the goal of this function is to set the device into verification mode. after recept ion of a valid enter_vmode command, mode opm5 is active. this command is only vali d in configuration mode (opm2). in case the request message is received while opm2 is not active, the complete command is discarded and an spi error occurs. table 2-6 describes the request message and the corresponding answer message. 2.4.4.5.5 exit_cmode command when a valid exit_cmode is received by the device, the configuration mode is left to configured mode (mode opm3 active). this command is only valid in configuration mode (opm2). in case the request message is received while opm2 is not active, the complete command is discardedand an spi error occurs. table 2-7 describes the request message and the corresponding answer message. < eicedriver ? sil 1EDI2002AS functional description datasheet 32 rev. 3.1, 2015-07-30 hardware description 2.4.4.5.6 nop command this command triggers no specific action in the driver (e quivalent to a ?nop?). however, the mechanisms verifying the validity of the word are active. this command is valid in all operating modes. table 2-8 describes the request message and the corresponding answer message. 2.4.4.5.7 read command this command aims at reading the value of the register whose address is specified in the request message. this command is valid in all o perating modes. however, in opm4 and opm6, the use of the read command is restricted (see table 4-3 ). if an access outside the allowed address range is performed, the access is discarded as invalid and an spi error occurs. table 2-9 describes the request message and the corresponding answer message. request message words word 1: ( address_5bit << 7 )] | 002a h | p b . answer message words word 1: value of register. 2.4.4.5.8 writeh this command aims at writing the upper byte of the inter nal write buffer with the s pecified value. this command has no other effect on the functionality of the device. this command is valid in all operating modes. table 2-10 describes the request message and the corresponding answer message. request message words word 1: 4400 h | ( data_8bit << 1 ) | p b table 2-8 nop request and answer messages transfer 1 transfer 2 request message 1410 h n.a. answer message n.a. va( pstat ) table 2-9 read request and answer messages transfer 1 transfer 2 request message see below n.a. answer message n.a. va(register) table 2-10 writeh request and answer messages transfer 1 transfer 2 request message see below n.a. answer message n.a. va( pstat )
eicedriver ? sil 1EDI2002AS functional description datasheet 33 rev. 3.1, 2015-07-30 hardware description 2.4.4.5.9 writel this command aims at updating the valu e of the register whose address is s pecified in the request message. this command is valid in all o perating modes. however, depending on th e active operating mode, this command is restricted to a given address r ange or specific registers (see table 4-4 ). if an access outside the allowed address range is performed, the access is discarded as invalid and an spi error occurs. at the reception of this command, the least significant byte of the internal buffer is wr itten with the specified value, the contents of the buffer is copied to the register at the specified address and the complete write buffer is cleared. table 2-11 describes the request message and the corresponding answer message. request message words word 1: a000 h | ( address_5bit << 7 ) | ( data_6bit << 1 ) | p b . table 2-11 writel request and answer messages transfer 1 transfer 2 request message see below n.a. answer message n.a. va( pstat )
eicedriver ? sil 1EDI2002AS functional description datasheet 34 rev. 3.1, 2015-07-30 hardware description 2.4.5 operating modes 2.4.5.1 general operation at any time, the driver can be in one out of seven possible operating modes: ? opm0: default mode (default after reset, device is disabled). ? opm1: error mode (reached after event class b, device is disabled). ? opm2: configuration mode (device is disabled , configuration of the device can be modified). ? opm3: configured mode (device is configured and disabled). ? opm4: active mode (normal operation). ? opm5: verification mode (intrusive di agnostic functions can be triggered). ? opm6: weak active mode (the device can be turned on but with restrictions) the current active mode of the device is given by bit field sstat . opm . the concept of the device is based on the following general ideas: ? the driver can only switch the ig bt on when opm4 mode is active (exception: weak-turn on in opm6). ? starting from mode opm0 or opm1 , the active mode opm4 can only be activated through a dedicated spi command sequence and the activation of the hardware signal en/fen . as a result, the probability that the device goes to opm4 mode due to random signals is negligible. ? differentiations of errors: different classes of errors are defined, leading to diffe rent behavior of the device. the state diagram for the operating modes is given in figure 2-11 : figure 2-11 operating modes state diagram opm0 default event ? class ? b opm5 ? verification opm4 ? active reset ? event event ? class ? a all ? res et ? events en ? valid ? transition opm2 configuration opm3 ? configured opm6 we ak ? active event ? class ? a en ? valid ? transition opm1 default event ? class ? breset ? event event ? class ? breset ? event event ? class ? breset ? event all ? event ? class ? b event ? class ? b cl rs ? set reset ? event event ? class ? b reset ? event
eicedriver ? sil 1EDI2002AS functional description datasheet 35 rev. 3.1, 2015-07-30 hardware description 2.4.5.2 definitions 2.4.5.2.1 events and state transitions the transitions from one state to the other are base d on ?events? and / or spi commands. the following classification is chosen for defining the events. events class a the following (exhaustive) list of ev ents are defined as events class a: ? occurrence of a desat event (lead s to a safe turn-off sequence). ? occurrence of an ocp event (leads to a safe turn-off sequence). ? valid to invalid transition on en/fen signal (leads to a regular turn-off sequence). ? tristate event due to an output stage monitoring event. ? tristate event due to the activation of signal osd . when an event class a occurs, the outp ut stage either initiate s either a safe turn-off sequence (desat, ocp, or a regular turn-off sequence ( en/fen event) or goes in tristate (tristate even t). the event is notified via an error bit in the corresponding register. note: contrarily to a reset event, an event class a does not affect the contents of the configuration registers. when an event class a occurs, the device may change its operating mode depending on which mode is active when the event occurs: ? if it was in opm4, it goes in opm3. ? if it was in opm6, it goes in opm5. in all other cases, the opm is unaffected. a state transition due to an event class a leads to the activation of signal nflta . if no state transition occurs (if for exam ple the device was not in opm4 or opm6), nflta is not activated (exception: tristate event - see chapter 2.4.7 for more details on failure notifications). events class b the following (exhaustive) list of ev ents are defined as events class b: ? occurrence of a uvlo2 event. ? occurrence of a ovlo2 event. ? occurrence of a uvlo3 event. ? occurrence of a ovlo3 event (with bit scfg2 . ovlo3d set). ? internal supervision error. ? verification mode time out error when an event class b occurs, the output stage initiates a regular turn-off sequence. the event is notified via an error bit in the corresponding regist er and (possibly) via the signal nfltb . note: events class b may affect the c ontents of the configuration registers. when an event class b occurs, the device may change its operating mode depending on which mode is active when the event occurs: if it was not in opm1 , it goes to opm1. it is unaffected otherwise a state transition due to an event class b leads to the activation of signal nfltb . if no state transition occurs (if for example the device was already in opm1), nfltb is not activated. see chapter 2.4.7 for more details on failure notifications.
eicedriver ? sil 1EDI2002AS functional description datasheet 36 rev. 3.1, 2015-07-30 hardware description events class c generally speaking, events class c are error events that do not lead to a change of the operating mode of the device. the following (non-exhaustive) list of events is comprised within the event class c: ? over temperature warning. ? spi error. ? shoot through protection error. ?etc. spi commands the following spi commands have an impact on the device ?s operating mode. the spi commands are described in chapter 2.4.4.5 . ? enter_cmode. ? enter_vmode. ? exit_cmode. ? setting of bit sctrl . clrs (by writing register pctrl ) reset events a reset sets the device (or part of the device) in its default state. reset events are described in chapter 2.4.9 . 2.4.5.2.2 emergen cy turn-off sequence the denomination ?emergency turn-off sequence? (eto) is used to describe the sequence of actions executed by the output stage of the device when an event class a (exception: tristate event) , class b or a reset event is detected. an eto sequence is described by the following set of actions: ? a turn-off sequence is init iated. in case of desat or ocp event, a safe turn-off se quence is initiated. for the other events, a regular turn-off sequence is initiated. ? the device enters the corresponding opm mode . as a consequence, the device is disabled. once an eto has been initiated, the device can not be reenabled for a maximum durat ion consisting of 256 osc2 clock cycles. consequently, the user shall wait for this duration before reenabling the device and sending pwm turn-on command. 2.4.5.2.3 ready, disabled, enabled and active state the device is said to be in ready st ate in case no reset event is active on the primary chip. when the device is ready, signal nrst/rdy is at high level. when the device is in disabled state, the pwm turn-o n commands are ignored. this means that whatever the input signal inp is, the output stage (if not tristated) deliver s a constant turn-off signal to the igbt. unless otherwise stated, all other functi ons of the device work normally. when the device is not in disabled state, it is said to be in enabled state. in this case, the pwm signal command is processed normally (if the output stage is not tristate d). practically, the device is in enabled state when either mode opm4 or mode opm6 is active. active state corresponds to the normal operating state of the device. practically , the device is in active state when mode opm4 is active.
eicedriver ? sil 1EDI2002AS functional description datasheet 37 rev. 3.1, 2015-07-30 hardware description note: when the device is in active state, it implicates it is in enabled state. 2.4.5.3 operation modes description default mode (opm0) mode opm0 is the default operating mo de of the device after power up or after a rest event. in opm0, the device is in disabled state. the following exhaustive list of events bring the device in opm0 mode: ? occurrence of a reset event. ?bit sctrl . clrs set while the device was in opm1. error mode (opm1) mode opm1 is the operating mode of the device after an event class b. the following exhaustive list of events bring the device in opm1 mode: ? occurrence of an event class b. in opm1, when bit sctrl . clrs is set via the corresponding spi co mmand, the device shall normally jump to opm0. however, in case the conditions for an event class b are met at that moment, no state transition occurs and the device stays in opm1. the operation of bit sctrl . clrs on the secondary sticky bits works normally. in opm1, when a valid enter_cmode command is re ceived, the device shall normally jump to opm2. however, in case the conditions for an event class b are met at that moment, no state transition occurs and the device stays in opm1 for the duration of the event. the state transition to opm2 is executed as soon as the conditions leading to the event class b disappear.it sha ll be noted that no lmi error notification is issued. configuration mode (opm2) configuration mode is the mode where the configuration of the device can be modified. when opm2 is active, the device is in disabled state. the following exhaustive list of events bring the device in configuration mode: ? reception of a valid enter_cmode command while mode opm0 or opm1 active. configured mode (opm3) configured mode is the mode where the device is ready to be enabled. when opm3 is active, the device is in disabled state. the following exhaustive list of events bring the device in mode opm3: ? reception of a valid exit_cmode command while mode opm2 active. ? event class a while mode opm4 active. active mode (opm4) the active mode corresponds to the normal operating mode of the device. when opm4 is active, the device is in active state. the following exhaustive list of event bring the device in active mode:
eicedriver ? sil 1EDI2002AS functional description datasheet 38 rev. 3.1, 2015-07-30 hardware description ? invalid to valid transition on signal en/fen while mode opm3 active. verification mode (opm5) verification mode is the mode where intrusive verificati on functions can be started. when opm5 is active, the device is in disabled state. the following exhaustive list of event bring the device in verification mode: ? reception of a valid enter_vmode command while mode opm2 active. ? occurrence of an event class a while mode opm6 active. after a transition from mode opm2 to opm5, an internal watchdog ti mer is started. if after time t vmto , the device has not left both modes opm5 or opm6, a time-out event occurs and an event class b is generated. weak active mode (opm6) weak active mode is the mode where the device can be ac tivated to run diagnosis tests at system level. when opm6 is active, the device is in enabled state. a pwm turn-on command issues a weak turn-on on the secondary side. the following exhaustive list of event bring the device in weak active mode: ? invalid to valid transition on signal en/fen while mode opm5 active. the watchdog counter started when entering mode opm5 is not reset when entering opm6. implementation notes related to state transitions ? an event class a or class b detected on the secondary si de lead to an immediate reaction of the device?s output stage. due to the latency of the inter-chip communicat ion, the notification on the primary side is slightly delayed. ? the activation of signal nflta or nfltb is simultaneous to the corresponding state transition on the primary side. ? it is possible to change the operating mode while a failu re condition is present. th is may however lead to a new immediate error notification and state transition. 2.4.5.4 activating the device after reset after a reset event, the device is in mode opm0 and disabl ed. in order to be active, the device needs to enter configuration mode with the enter_cm ode command. once all the configurations have been performed, the configuration mode has to be exited with an exit_cm ode command. once this is done, the device can enter the active mode when invalid to valid transition on pin en/fen is detected. 2.4.5.5 activating the device after an event class a or b if during operation, an event class a occurs, th e device enters the opm3 (or opm5). bit field sstat . opm is updated accordingly. in order to reactivate the device, an invalid-to-valid transition has to be applied to signal en/fen . it means for example in en mode, that a lo w-level and then a high level is applied to en/fen . if no event class a event is active, the devi ce will enter opm4 (respectively opm6). if during operation, an event class b occurs, the device enters the default mode opm1. bit field sstat . opm is updated accordingly. in order to reacti vate the device, the steps defined in chapter 2.4.5.4 need to be performed.
eicedriver ? sil 1EDI2002AS functional description datasheet 39 rev. 3.1, 2015-07-30 hardware description 2.4.5.6 debug mode the debug pin gives the possibility to operate the device in the so-called debug mode . the goal of the debug mode is to operate the device without spi interface. this mode should be used for development purpose only and is not intended to be used in final applications. at v cc2 power-on, the level at pin debug is latched. in case a high level is detected, the device enters the debug mode. bit sstat . dbg is then set. in debug mode, the regular operation of the internal stat e machine is modified, so t hat the device can only enter opm3 or opm4. as a result modes opm0, opm1, opm2 , opm5 and opm6 are completely bypassed. in case of a reset event, the device goes to opm3 (instead of opm0). besides, in debug mode, events leading normally to an event class b are replaced an event class a, resulting in the activation of signal nflta . event class b are therefore not generated by the device in debug mode (and signal nfltb shall not be used). it should be noted that the configurat ion of the device in debug mode corresponds to the default settings and can not be changed (for example, the desat function is completely deactivated). in debug mode, the operation of the devic e is otherwise similar to regular operat ion. it means in particular that the signal en/fen has to be managed properly: when the device is in opm3, a low to high level transition has to be applied to the device in order to enter opm4 (active mode). note: once it has been latched at power-on, the level on the pin debug has no impact on the device until the next power-on event on the secondary side.
eicedriver ? sil 1EDI2002AS functional description datasheet 40 rev. 3.1, 2015-07-30 hardware description 2.4.6 driver functionality the structure of the output stage and its associat ed external booster of the device is depicted figure 2-12 : figure 2-12 output stage diagram of principle 2.4.6.1 overview two turn-off behaviors are supported by the device, depending on the event causing the turn-off action. ? regular turn-off. ? safe turn-off. a safe turn-off sequence uses the timing and plateau level parameters defined in register ssttof . it is triggered by a desat or an ocp event only. a turn-o ff sequence which is no t ?safe? is then ?regul ar?. a regular turn-off sequence uses the timing para meters defined in register srttof and the plateau level defined by sctrl . gpofs . two level turn-off (ttoff) because a hard turn-off may generate a critical overvoltage on the igbt leading eventually to its destruction, the 1EDI2002AS supports the two level turn-off functionalit y (ttoff). the ttoff function consists in switching the igbt off in three st eps in such a way that: 1. the igbt gate voltage is first decreased with a reduced slew rate until a specific (and programmable) voltage is reached by the toff signal. 2. toff (and ton ) voltage is stabilized at this level. the igbt gate voltage forms thus a plateau. 3. finally, the switch-off sequence is resumed using hard commutation. the ttoff delays and plateau voltage are fully programmable using the corresponding spi commands. for a regular turn-off sequence, the ttoff delay is defined by bit field srttof . rtval . setting this field to 00 h completely disables the ttoff function fo r all regular turn-off sequences (but this has no effect on safe turn- off sequences). the plateau level is defined by sctrl . gpofs . if this function is to be activated, a minimum value for the delay time has to be programmed. vcc2 toff gate ? driver daclp ton gate r on r off vgnd2 vee2
eicedriver ? sil 1EDI2002AS functional description datasheet 41 rev. 3.1, 2015-07-30 hardware description for a safe turn-off sequence, the ttoff delay is defined by bit field ssttof . stval . setting this field to 00 h completely disables the ttoff function for all safe turn-o ff sequences (but this has no effect on regular turn- off sequences). if this function is to be activated, a minimum value for the delay time has to be programmed. the plateau level is defined by ssttof . gps . the timing of a safe turn-o ff event is in the clock doma in of the main secondary o scillator (osc2). the timing of a regular turn-off ev ent is in the clock domain of the start-stop oscillator (sso sc2), leading to high accuracy and low pwm distortion when using the ttoff function (with a non-zero delay), the pwm command is received on pin inp is delayed by the programmed delay time ( figure 2-13 ). for pulses larger than the ttoff delay (t pulse > t ttoff +two ssosc cycles), the output pulse width is kept identical to the input pulse wid th. for smaller pulses (t pulse < t ttoff +2 two ssosc cycles), the output pulse is identical to the progr ammed delay. the minimum pulse width delivered by the device to the igbt is therefore the progra mmed delay time extended by two ssosc cycles. the device allows for external booster voltage compensation at the igbt gate. when bit scfg . vbec is cleared, the voltage at toff at the plateau corresponds to the programmed value. when bit scfg . vbec is set, an additional v be (base emitter junction voltage of an internal pn diode) is substracted from the programmed voltage at toff in order to compensate for the v be of an external booster.
eicedriver ? sil 1EDI2002AS functional description datasheet 42 rev. 3.1, 2015-07-30 hardware description figure 2-13 ttoff: principle of operation two level turn-on (tton) in order to increase em compatibility and the effici ency of the whole system, th e 1EDI2002AS supp orts the two level turn-on functionality (tton). th e tton function consists in switching the igbt on in three steps in such a way that: 1. the igbt gate voltage is first increased until a spec ific (and programmable) voltage is reached by the ton signal. 2. ton (and toff ) voltage is stabilized at this level. the igbt gate voltage forms thus a plateau. 3. finally, the switch-on sequence is resu med up to the maximum output voltage. the tton feature needs to be activated by configuring the delay with bit field scfg2 . ttond . t pulse < t ttoff + 2. t ssosc t pdon t ttoff t ttoff input pulse output pulse t pulse > t ttoff + 2. t ssosc t pdon t ttoff t pulse t pdoff t ttoff input pulse output pulse ttoff plateau a) b) 2. t ssosc
eicedriver ? sil 1EDI2002AS functional description datasheet 43 rev. 3.1, 2015-07-30 hardware description the plateau voltage level can be configured during run time by updating bit field sctrl . gpons . this bit field can also be programmed to a value generating a hard turn-on. when using the tton function (with a non-zero delay), the pwm command is received on pin inp is not delayed by the programmed tton delay time ( figure 2-14 ). however, the minimum pulse width that can be generated corresponds to the programmed tton delay. thus, for input pulses smaller than the tton delay (t pulse < t tton ), the output pulse width is extended. the device allows for external booster voltag e compensation at the igbt gate. when bit scfg2 . vbec is cleared, the voltage at ton at the plateau corresponds to the programmed value. when bit scfg2 . vbec is set, an additional v be (base emitter junction voltage of an internal pn diode) is added to the programmed voltage at ton in order to compensate for the v be of an external booster. the ton and ttoff functions can be used simultaneously. figure 2-14 tton: principle of operation t pulse < t tton t pdon input pulse output pulse tton plateau a) b) t pulse > t tton t pdon t tton t pulse t pdoff input pulse output pulse t tton
eicedriver ? sil 1EDI2002AS functional description datasheet 44 rev. 3.1, 2015-07-30 hardware description pulse suppressor in order to increase the device?s robustness against ex ternal disturbances, a pulse suppressor can be enabled by setting bit scfg . psen . register srttof shall also programmed with a value higher than 2 h . when a pwm turn- on sequence occurs, the activation of the output st age is delayed by the programmed ttoff number of cycles, as for a normal ttoff sequence. however, the pwm command received by the secondary chip signal is internally sampled at every ssosc cycle before the actual turn-on command is executed by the output stage. if at least one of the sampling point does not detect a high level, the turn-on sequence is aborted and the device is not switched on. in case a valid pwm on command is detected by the secondary side after the decision point the previous sequence has been aborted, a new turn-on sequence is initiated. one of the consequence of activating the pulse suppre ssor is that all pwm pulses shorter than the programmed ttoff plateau time are filtered out ( figure 2-15 ). note: the pulse suppressor only acts on turn-on pulses, not on turn-off pulses. figure 2-15 ttoff: pulse suppressor aborting a turn-on sequence t pulse < t ttoff + 2 . t ssosc input pulse output pulse pulse filtered out scfg.psen=1b
eicedriver ? sil 1EDI2002AS functional description datasheet 45 rev. 3.1, 2015-07-30 hardware description 2.4.6.2 switching sequence description figure 2-16 shows an idealized switching sequence. when a valid turn-on command is detected, a certain propagation time t pdon is needed by the logic to tr ansfer the pwm command to the secondary side. at this point the ttoff delay time t ttoff defined by bit field srttof . rtval is added before the turn-on command is executed. signal ton is then activated, while signal toff is deactivated. in case the two level turn-on function is active, signal to n is increased up to the plateau voltage defined by bit field sctrl . gpons . the duration t tton between the beginning of the turn-on sequence and the moment where the switching sequence is resu med is defined by bit field scfg2 . ttond . when a valid turn-off command is detected, a certain propagation time t doff is needed by the command to be processed by the logic on the secondary side. this pr opagation time depends on the event having generated the turn-off action (non exhaustive list): ? in case of a pwm turn-off command at pin inp , t doff =t pdoff . ? in case of a desat event, t doff =t offdesat2 . ? in case of an ocp event, t doff =t offocp2 . ? in case of an event class a on the primary side: t doff =t offcla . ? in case of an event class b on the secondary side: t doff =t offclb2 . when the turn-off command is pr ocessed by the logic, signal daclp is deactivated (i.e. active clamping is enabled). signal ton and toff are decreased with the slew rate t slew fixed by hardware. once the voltage at pin toff has reached the value defined by bit field sctrl . gpofs (or ssttof . gps in the case of a safe turn- off), the turn-off sequence is interrupted. time t ttoff is defined as the moment when the device starts turning off signal toff , and the moment where the turn-off sequence is resumed. depending on the event that triggered the turn-off sequence, t ttoff is given by either bit field srttof . rtval or ssttof . stval . once the ttoff time has elapsed, a hard commutation takes place, and signals ton and toff are driven to v ee2 . note: once a turn-off sequen ce is started, it is completed to the end with the same delay parameters. at the moment when the hard commutation takes place, signal daclp remains deactiva ted for time t acl defined by bit field saclt . at . when this time is elapsed, signal daclp is reactivated (i.e. acti ve clamping is disabled). when bit scfg2 . aclpm is set, signal daclp is only deactivated in case of a safe turn-off sequ ence, for a total duration t acl (+ t ttoff , if applicable). in case saclt . at is set to 0 h , daclp is constantly activated (c onstant high level). in case saclt . at is set to ff h , daclp is constantly at low level. the gate monitoring function (time-out mechanism) is started at each turn-on and turn-off sequence. see chapter 3.4.2 for more details.
eicedriver ? sil 1EDI2002AS functional description datasheet 46 rev. 3.1, 2015-07-30 hardware description figure 2-16 idealized switching sequence v gate v ton v ee2 v ee2 v toff v cc2 v ee2 turn-on event t pdon t ttoff time time time 5v gnd2 v daclp time ~ ~ turn-off event t doff t ttoff ~ ~ v cc2 v cc2 v gtofx ~ ~ ~ ~ t acl v gate1 v gate2 t tton v gponx
eicedriver ? sil 1EDI2002AS functional description datasheet 47 rev. 3.1, 2015-07-30 hardware description 2.4.6.3 disabling the output stage the output stage of the device can be disabled, i.e. tristated. there are two ways to tristate the device: either via signal osd or via the output stage monitor (see chapter 3.2.4 ). the current state of the output stage is indicated by bit sstat . hz . if the bit is cleared, the output stage operates normally and issues a high or a low level. if it is set, signals ton and toff are tristated. if the transition from normal operation to tristate is caused by the output stage monitoring, an event class a is generated. if it is caused by a high level detected on pin osd , an event class a is generated only if bit scfg . osdad is cleared. otherwise, if scfg . osdad is set, no event is generated (i.e opm mode not changed). when bit sstat . hz is set, sticky bit ser . oster is set (independently from the value of scfg . osdad ). figure 2-17 shows the principle of operation of the output stage disable mechanisms. the activation of signal nflta due to a tristate event depends on the configuration of the chip (see chapter 2.4.7 ). figure 2-17 output stage disable: principle of operation note: bit sstat . hz is the result of the logical operation of bit sctrl . ostc being ored with bit sstat2 . osdl . osd signal the input signal osd is used as a control signal in order to trista te the output stage of the device. a low level at pin osd corresponds to the normal operat ion of the device. when signal osd is at high level, the output stage is tristated. a high to low transition of signal osd clears bit sctrl . ostc . the level read by the device at pin osd is given by bit sstat2 . osdl . output stage monitoring the output stage monitoring function is described in chapter 3.2.4 . in case the osm detects an error condition, bit sctrl . ostc is set and the output stage is tristated. the functionality of the osm is controlled by bit scfg . osmd . when this bit is se t, the osm is inhibited. 2.4.6.4 passive clamping when the secondary chip is not supplied, signals toff , ton and gate are clamped to v ee2 . see chapter 5.5.4 for the electrical capa bility of this feature. osm event s r or sctrl.ostc sstat.hz ser.oster s r event class a osd level clrs or and scfg.osmd or scfg.osdad and
eicedriver ? sil 1EDI2002AS functional description datasheet 48 rev. 3.1, 2015-07-30 hardware description 2.4.7 fault notifications the device provides two kinds of fault notification mechanisms: ?pins nflta , nfltb and nrst/rdy allow for fast error notification to th e main microcontroller. all signals are active low. ? error bits can be read by spi. the activation of signal nrst/rdy is associated with reset events (see chapter 2.4.9 ). the activation of signal nflta is associated with class a ev ents. the activation of signal nfltb is associated with class b events. in general the activation of signal nflta or nfltb is linked to a state transition of the state machine. if an event class a occurs that leads to a state transition (from opm4 to opm3 or opm6 to opm5), signal nflta is activated. in case an event class a occu rs that does not lead to a state transition, nflta is not activated (exception: tristate events). however, t he corresponding error bit in register per or ser is set. tristate events are handled in a special way. tristate events can be generated either by the output stage monitoring (when enabled) or by a high level at pin osd . in case bit scfg . osmd is set, the osm is completely disabled and therefore can not generate any tristate events (and consequently it can not generate events class a). in case bit scfg . osdad is set, a transition to high level of pin osd does not generate any state transition. as a result, no event class a is generated. however, bit ser . oster is set and the output stage is in tristate for the duration for which pin osd is at high level. additionally, signal nflta can be activated directly by the status bits on the primary side.this allows to have signal nflta activated in any opm mode in case of tristate events. if pcfg . ostaen is set, nflta is activated at the transition of bit per . oster from 0 b to 1 b . if pcfg . osmaen is set, nflta is activated at the transition of bit pstat2 . ostc from 0 b to 1 b . in case both bits pcfg . ostaen and pcfg . osmaen are cleared, nflta is only activated in case of a stat e transition of the state machine. if an event class b occurs that leads to a state transition (to opm1), signal nfltb is activated. in case an event class b occurs that does not lead to a state transition, nfltb is not activated. however, the corresponding error bit in register per or ser is set. ovlo3 events are handheld in a special way. in case bit scfg2 . ovlo3d is set, an ovlo3 event does not lead to a transition of the state machine ( nfltb is not activated). besides, no emergency turn-off sequence is initiated. however, bit ser . ovlo3er is set. therefore, when bit scfg2 . ovlo3d is set, ovlo3 detection mechanism behaves like an event class c. table 2-12 describes how failure notifications are cleared: the level issued by the device on pins nflta and nfltb is given by bits pstat2 . flta and pstat2 . fltb . the levels read by the device at those pins is given by bits ppin . nfltal and ppin . nfltbl . table 2-12 failure notification clearing nflta / b signals primary sticky bits secondary sticky bits pctrl . clrp set de-assertion cleared - pctrl . clrs set 1) 1)if the device is in opm1, setting bit sctrl . clrs leads to a transition to opm0 - - cleared en/fen invalid to valid tr ansition de-assertion 2) 2) only in opm3 and opm5. in other op erating modes, no de-assertion is done. --
eicedriver ? sil 1EDI2002AS functional description datasheet 49 rev. 3.1, 2015-07-30 hardware description 2.4.8 en signal pin the en/fen signal allows the logic on the primary side to have a direct control on the state of the device. a valid signal has to be provided on this pin. a valid to invalid transition of the signal on pin en/fen generates an event class a. pin en/fen should be driven actively by the external circuit. in case this pin is floating, an internal weak pull-down resistor ensures that the signal is low. note: it should be noted that even if the signal at pin en/fen is valid, the device can still be in disabled state. this may happen for example if another error is being detected depending on the value of bit pcfg2 . fen , two types of valid signals can be chosen from: en mode when the en mode is selected (bit pcfg2 . fen cleared), pin en/fen acts as an enable pin. a valid en/fen signal is defined as a digital high level. when en/fen is at low level, the signal is considered as not valid and the device is in disabled state. in case of a high-to-low transi tion, an event class a is generated. fen mode when the fen mode (bit pcfg2 . fen set) is selected, a valid signal is defined as a periodic clock signal. the signal is constantly monitored by a watchdog unit. the watc hdog evaluates the signal as valid if two consecutive valid half-periods are detected. if, after a valid signal has been recognized, a timing vi olation is detected by the watchdog, an event class a is generated. every time an edge (rising or falling) is received, a coun ter is started. the counter is incremented at a frequency of f osc1 /8. the following edge is expected by the device duri ng a window corresponding to the time between state 2 and state 6 of the counter. in case the edge comes too early or too late, an event class a is generated. an invalid to valid transition of signal en/fen deactivates signals nflta and nfltb (when the device is in opm3 or opm5 only). the levels read by the device at pin en/fen is given by bits ppin . enl . the validity status of en/fen signal is given by bit pstat2 . enval . 2.4.9 reset events a reset event sets the device and its internal logic in the default configuration. all user-defined settings are overwritten with the default values. the list of re set events and their effect is summarized in table 2-13 .
eicedriver ? sil 1EDI2002AS functional description datasheet 50 rev. 3.1, 2015-07-30 hardware description table 2-13 reset events summary reset event primary secondary notification (primary) notification (secondary) nrst/rdy input signal active (driven externally) reset soft reset ? nrst/rdy low (during event). ?bit per . rste1 and per . rst1 set. ?bit per . cer1 is not set. ? event class b ( nfltb activated) at the end of the reset event. ?bit ser . cer2 set (in case of lifesign lost). ? output stage issues a pwm off command. ? osd pin functionality operational. uvlo1 event reset soft reset ? nrst/rdy low (driven by device during event). ?bit per . rst1 set (once v cc1 valid again). ?bit per . cer1 is not set. ? event class b ( nfltb activated) at the end of the reset event. ?bit ser . cer2 set (in case of lifesign lost). ? output stage issues a pwm off command. ? osd pin functionality operational. osc1 not starting at power-up reset soft reset ? nrst/rdy low (driven by device during event). ?bit per . rst1 set (once osc1 valid again). ?bit per . cer1 is not set. ? event class b ( nfltb activated) at the end of the reset event. ?bit ser . cer2 set (in case of lifesign lost). ? output stage issues a pwm off command. ? osd pin functionality operational. iref1 shorted to ground or open reset soft reset ? nrst/rdy low (driven by device during event). ?bit per . rst1 set (once iref1 valid again). ?bit per . cer1 is not set. ? event class b ( nfltb activated) at the end of the reset event. ?bit ser . cer2 set (in case of lifesign lost). ? output stage issues a pwm off command. ? osd pin functionality operational. memory error on primary reset soft reset ? nrst/rdy low (driven by device during event). ?bit per . rst1 set (when failure condition is removed). ?bit per . cer1 is not set. ? event class b ( nfltb activated) at the end of the reset event. ?bit ser . cer2 set (in case of lifesign lost). ? output stage issues a pwm off command. ? osd pin functionality operational.
eicedriver ? sil 1EDI2002AS functional description datasheet 51 rev. 3.1, 2015-07-30 hardware description all reset events set the device in mo de opm0. in a soft reset, the logic works further, but the registers use the default values. in case of a reset condition on the primary side, th e behavior of the pin of the device is defined in table 2-14 . uvlo2 event - hard reset ? event class b ( nfltb activated, bit per . cer1 set). ?bit pstat . srdy cleared for the duration of the failure. ? signal nuv2 at low level (if v cc2 v rst2 . osc2 not starting at power-up - hard reset ? event class b ( nfltb activated, bit per . cer1 set) ?bit pstat . srdy cleared ? output stage issues a pwm off command. ? osd pin functionality operational. osc2 misfunction during operation -soft reset ? event class b ( nfltb activated, bit per . cer1 set) ?bit pstat . srdy cleared for the duration of the failure. ? output stage issues a pwm off command. ? osd pin functionality operational. iref2 open - hard reset ? event class b ( nfltb activated, bit per . cer1 not) ?bit pstat . srdy cleared none. vreg shorted to ground - undefined ? event class b ( nfltb activated, bit per . cer1 set) ?bit pstat . srdy cleared. ? signal nuv2 at low level. ? output stage issues a pwm off command. memory error on secondary - hard reset ? event class b ( nfltb activated, bit per . cer1 set). ?bit pstat . srdy cleared. ? output stage issues a pwm off command. ? osd pin functionality operational. table 2-14 pin behavior (primary side) in case of reset condition pin output level comments sdo low dout tristate nfltb low nflta high nrst/rdy low (gnd1) table 2-13 reset events summary reset event primary secondary notification (primary) notification (secondary)
eicedriver ? sil 1EDI2002AS functional description datasheet 52 rev. 3.1, 2015-07-30 hardware description in case of a hard reset condition on the secondary si de, the behavior of the pin of the device is defined in table 2-15 . 2.4.10 operation in configuration mode this section describes the mech anisms to configure the device. 2.4.10.1 static configuration parameters static parameters can configured when the device is in mode opm2 by writing the appropriate register. once mode opm2 is left with the sp i command exit_cmode, the configuration parameters are frozen on both primary and secondary chips. this means in particular that write accesses to the corresponding registers are invalidated. this prevents static conf igurations to be modified during runtime. besides, the configuration parameters on the primaryand secondary side are protected with a memory protection mechanism. in case the values are not consistent, a reset event and / or an event class b is generated. 2.4.10.1.1 configuration of the spi parity check the spi interface supports by default an odd parity check. the parity check mechanism (active at the reception of an spi word) can be disabled by setting bit pcfg . paren to 0 b . setting bit paren to 1 b enables the parity check. parity bit generation for the transmitter can not be disabled. 2.4.10.1.2 configuration of nflta acti vation in case of tristate event signal nflta is normally activated by a state transition of th e internal state machine. however, it can be also configured to be activated in relation with the primary bits per . oster or pstat2 . ostc . this is configured thanks to bits pcfg . ostaen and pcfg . osmaen . 2.4.10.1.3 configuration of the stp minimum dead time the minimum dead time for the shoot-through prot ection can be programmed by writing bit field pcfg2 . stpdel . the value programmed corresponds to a number of osc1 clock cycles. note: register pcfg2 can only be written if bit pcfg . cfg1 is set. table 2-15 pin behavior (secondary side) in case of reset condition pin output level comments ton low (v ee2 ) passive clamping toff low (v ee2 ) passive clamping desat low (gnd2) clamped. gate low (v ee2 ) passive clamping daclp high (5v) active clamping disabled by default. nuv2 low (gnd2)
eicedriver ? sil 1EDI2002AS functional description datasheet 53 rev. 3.1, 2015-07-30 hardware description 2.4.10.1.4 configuration of the en/fen mode the mode of operation of pin en/fen can be programmed by writing bit field pcfg2 . fen . the description of the operating modes is given in chapter 2.4.8 . note: register pcfg2 can only be written if bit pcfg . cfg1 is set. 2.4.10.1.5 configuration of the digital channel the direction of pin dio1 can be programmed by writing bit field pcfg2 . dio1 . the direction of pin dio2 can be programmed by writing bit field scfg2 . dio2 . note: register pcfg2 can only be written if bit pcfg . cfg1 is set. register scfg2 can only be written if bit scfg . cfg2 is set. 2.4.10.1.6 configuration of dout signal activation the signal at pin dout can be activated or deac tivated by programming bit pcfg2 . doen1 . if deactivated, pin dout delivers a steady low signal. the rest of the logi c is not affected by this setting. besides, bit scfg2 . ismen has to be set as well. furt hermore, perm anent desat clamping s hall be deactivated ( scfg . dstcen cleared). note: register pcfg2 can only be written if bit pcfg . cfg1 is set. register scfg2 can only be written if bit scfg . cfg2 is set 2.4.10.1.7 configuration of the v be compensation the v be compensation of signal ton and toff can be activated or deactivated by writing bit scfg . vbec . see chapter 2.4.6 for more details. 2.4.10.1.8 deactivation of output stage monitoring the osm function can be disabled by setting bit scfg . osmd . 2.4.10.1.9 deactivation of events class a due to pin osd by setting bit scfg . osdad , event class a are not issued in case of a tristate event generated by pin osd . other actions such as tristating th e output stage or setting bit ser . oster are performed normally. 2.4.10.1.10 clamping of desat pin by setting bit scfg . dstcen , the desat signal is clamped to v gnd2 while the output stage of the device issues a pwm off command and during blanking time periods. by clearing bit scfg . dstcen , the desat clamping is only activated during blanking time periods. in order to use the igbt monitoring function, bit scfg . dstcen shall be cleared.
eicedriver ? sil 1EDI2002AS functional description datasheet 54 rev. 3.1, 2015-07-30 hardware description 2.4.10.1.11 activation of the pulse suppressor the pulse suppressor function associated with the ttoff function can be activated by setting bit scfg . psen . when activated, srttof . rtval shall be programmed with a minimum value (see page 119 ). 2.4.10.1.12 configuration of the ve rification mode time out duration the duration of the time out in ve rification mode is selectable via bit scfg . tosen . 2.4.10.1.13 desat threshold level configuration by writing bit field scfg2 . dsatl , it is possible to select the detection level of the desat comparator (which is also the level for the dout function). note: register scfg2 can only be written if bit scfg . cfg2 is set. 2.4.10.1.14 configurati on of the tton delay the tton delay can be configured by writing bit field scfg2 . ttond . programming 0 h as a delay value disables the tton for all turn-on sequences. hard turn-on are perfor med instead. in case the tton function is wished, a minimum value for the delay has to be programmed (see page 112 ). the tton delay can be calibrated using the tcf feature of the device. note: register scfg2 can only be written if bit scfg . cfg2 is set. 2.4.10.1.15 configuration of daclp activation mode the daclp activation mode can be programmed by writing bit scfg2 . aclpm . when this bit is cleared, signal daclp is deactivated at every turn-off sequence (with the programmed activation time). when it is set, daclp is deactivated only in case of an emer gency turn-off sequence. note: register scfg2 can only be written if bit scfg . cfg2 is set. 2.4.10.1.16 ovlo3 operation mode the activation mode of the ovlo3 functi on can be selected by programming bit scfg2 . ovlo3d . when this bit is cleared, an event class b is ge nerated in case on a ovlo3 event (v ee2 above a given threshold). when this bit is set, no event class b is generated in case of an ovlo3 event, but an event class c: the opm mode is not affected, the output stage is not turned off and signal nfltb is not activated. nevertheless, bit ser . ovlo3er is set (and mirrored to per . ovlo3er ). note: register scfg2 can only be written if bit scfg . cfg2 is set. 2.4.10.1.17 configurati on of the ttoff delays the ttoff delays for regular and safe turn-off sequences can be programmed separately by writing registers srttof or ssttof . the delay for regular turn-off can also be configured using the timing calibration feature.
eicedriver ? sil 1EDI2002AS functional description datasheet 55 rev. 3.1, 2015-07-30 hardware description programming 0 h as a delay value disables the ttoff for the concerned turn-off sequence. hard turn-off are performed instead. in case the tto ff function is wished, a minimum value for the delay has to be programmed (see page 119 and page 120 ). when safe two level turn-off is used (non zero delay) in normal operating mode (opm4), the programmed safe turn-off delay value shall be higher than the programmed regular two level turn off delay. 2.4.10.1.18 configuration of the safe ttoff plateau level the plateau level for safe two level turn off sequences can be programmed with bit field ssttof . gps . the plateau level value for safe turn-off sequences shall be lower than the one selected for regular turn-off sequences. 2.4.10.1.19 configuration of the desat blanking time the blanking time for the desat protection can be configured by writing bit field sdesat . dsatbt . in case this function is used, a minimum value fo r the delay has to be programmed (see page 117 ). note: the programmed ocp blanking time shall be smaller than the programmed desat blanking time. 2.4.10.1.20 configuration of the ocp blanking time the blanking time for the ocp protection can be configured by writing bit field socp . ocpbt . programming 0 h deactivates the blanking time featur e. the programmed blanking time shall not exceed a maximum value (see page 118 ). note: the programmed ocp blanking time shall be smaller than the programmed desat blanking time. 2.4.10.1.21 configuration of daclp activation time the daclp activation time after hard commutation can be programmed by writing bit field saclt . at . in case value 0 h is programmed, the device delivers at daclp a constant high level. in case an activation time is required, a minimum value for the delay has to be programmed (see page 123 ). in case value ff h is programmed, the device delivers a constant low level at daclp . 2.4.10.2 dynamic configuration the ttoff plateau level in regular turn-off can be modified during runtime by writing bit field pctrl2 . gpof . the value of this bit field is periodically transferred to the secondary side. the last valid received value by the primary side is available at bit field pstat . gpofs . the value currently used by the seco ndary chip is available at bit field sctrl . gpofs . the ttoff plateau for safe turn-off can only be configured statically with bit field ssttof . gps . this dynamic configuration of the pl ateau level allows to compensate for temperature variations of the i-v characteristic of the igbt. in over current conditions, the maximum current flowing through the igbt when the plateau is reached can be limited more accurately. similarly, the wtoand the tton plateau leve l can be configured by writing bit field pctrl . gpon . the plateau value stored in the devi ce at the beginning of the correspo nding switching sequence is latched and active until the next switching sequence.
eicedriver ? sil 1EDI2002AS functional description datasheet 56 rev. 3.1, 2015-07-30 hardware description 2.4.10.3 delay calibration in order to compensate for timing errors due to part-to-part variations, a dedicated timing calibration feature (tcf) has been implemented. the tcf works in such a way that the pwm input signal is used to start and stop a counter clocked by the start-stop o scillator of the output stage. as a re sult, the following delays and timing can be configured that way: ? ttoff delay for regular turn-off. ? tton delay. the tcf allows to compensate for part to part variations of the frequency of the start- stop oscillator. this results in better accuracy for applic ation critical timing. device specific vari ations, e.g. temperature related, are not compensated though. the tcf can be activated or deactivated in configuration mode by writing bit field sscr . vfs2 . the device shall then be set in opm6 and the pwm signal applie d. details about the tcf operation are given in chapter 3.5.9 .
eicedriver ? sil 1EDI2002AS functional description datasheet 57 rev. 3.1, 2015-07-30 hardware description 2.4.11 low latency digital channel the low latency digital channel aims at providing an alternative to discrete galvanic isolators. digital signals can be transmitted through pins dio1 and dio2 . the direction of the channel is given by bit field pcfg2 . dio1 and scfg2 . dio2 . the functionality of the channel is shown figure 2-18 . figure 2-18 low latency digital channel the voltage level at pin dio1 can be read at bit ppin . dio1l . the voltage level at pin dio2 can be read at bit sstat2 . dio2l . the input stages of signals dio1 and dio2 include each a debouncing filter. the input signals are that way filtered from glitches an d noise (mini-filter of two consecutive osc2 cycles). dio1 output, dio2 input dio2 t dspon time t dspoff dio1 dio1 input, dio2 output dio1 t dpson time t dpsoff dio2
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 58 rev. 3.1, 2015-07-30 hardware description 3 protection and diagnostics this section can describes the safety releva nt functions implemented in the 1EDI2002AS. 3.1 supervision overview the 1EDI2002AS driver provides ex tended supervision functions, in or der to achieve asil requirements on system level. table 3-1 gives an overview of the implemented functions. table 3-1 safety related functions protection feature description cate- gory comments desat monitoring of the collector-e mitter voltage of the igbt in on state. asee chapter 3.2.1 ocp monitoring of the current on the igbt?s auxiliary emitter path. asee chapter 3.2.2 external enable fast deactivation via an external enable signal on the primary. asee chapter 3.2.3 output stage monitoring monitoring of ton and toff signals. a see chapter 3.2.4 power supply monitoring under voltage lock-out function on v cc1 , v cc2 and v ee2 ; over voltage lock-out on v ee2 and v cc2 . bsee chapter 3.3.1 internal supervision monitoring of the ke y internal functions of the chip. b see chapter 3.3.2 stp shoot through protection. c see chapter 3.4.1 gate monitoring monitoring of the gate voltage during a switching sequence. csee chapter 3.4.2 temperature monitoring over temperature warning for the driver. c see chapter 3.4.3 spi error detection spi error detection. c see chapter 3.4.4 active short circuit support v cc2 not valid error notification c see chapter 3.4.5 igbt state monitoring the current state of the igbt is given by signal dout .c see chapter 3.4.6 wto weak turn-on functionality d see chapter 3.5.2 desat supervision supervision of the desat function during application life time. dsee chapter 3.5.3 , chapter 3.5.4 and chapter 3.5.5 ocp supervision supervision of the oc p function during application life time. c & d see chapter 3.5.6 , chapter 3.5.7 and chapter 3.2.2 power supply monitoring supervision supervision of the ovlo / uvlo function during application life time. dsee chapter 3.5.8
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 59 rev. 3.1, 2015-07-30 hardware description from the conceptual point of view, the protection functions can be clus tered into five main categories. ? category a corresponds to the functions where the device ?decides on its own?, after the detection of an event class a, to change the state of the output stage and to di sable itself. a dedicated action from the user is needed to reactivate the device (fast reactivation). ? category b corresponds to the functions where the device ?decides on its own?, after the detection of an event class b, to change the state of the output stage and to di sable itself. a complete rein itialization from the user is needed to reactivate the device (slow reactivation). ? category c corresponds to the functions that only issue a notification in case an error is detected. ? category d are intrusive supervision functions, aimed at being started wh en the application is not running. ? category e corresponds to implemented functions or capabilit ies supported by the device whose use can enhance the overall safety coverage of the application. internal clock supervision plausibility check of the fr equency of the internal oscillator. dsee chapter 3.5.9 dio supervision supervision of the dio channel d see chapter 3.5.10 ttoff two level turn-off e see chapter 2.4.6 spi communication spi communication (using register prw ). e see chapter 4.1 overvoltage robustness robustness agai nst transient overvoltage on power supply. esee chapter 5.2 table 3-1 safety related functions (cont?d) protection feature description cate- gory comments
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 60 rev. 3.1, 2015-07-30 hardware description 3.2 protection functions: category a 3.2.1 desaturation protection the integrated desaturation (desat) functionality is summarized in table 3-2 : the desat function aims at protec ting the igbt in case of short circuit. the voltage drop v ce over the igbt is monitored via the desat pin while the device issues a pwm on command. the voltage at pin desat is externally filtered by an exte rnal rc filter, and decoupled by an external diode (see figure 3-1 ).the desat voltage is compared to an internal reference voltage. the result of this comparison is available by reading bit sstat2 . dsatc . figure 3-1 desat function: diagram of principle at the beginning of a turn-on sequence, the vo ltage at pin desat is forced to low leve l for the duration the blanking time defined by register sdesat . once the blanking time has elapsed, the voltage at pin desat is released and is compared to an internal reference volta ge. depending on the value of the decoupling capacitance, an additional ?analog? blanking time will be added corresponding to the char ging of the capacitance through the internal pull-up resistance ( figure 3-2 ). in case the measured voltage is higher than the select ed internal threshold, an emergency (safe) turn-off sequence is initiated, bit ser . desater is set and a fault notification is issued on pin nflta (in case of an opm transition the state machine - see chapter 2.4.7 ). table 3-2 desat protection overview parameter short description function monitoring of the v ce voltage of the igbt. periodicity continuous while device issues a pwm on command. action in case of failure event 1. emergency (safe) turn-off sequence. 2. error flag ser . desater is set. 3. assertion of signal nflta . programmability yes (blanking ti me and detection threshold). in-system testability yes (see also chapter 3.5.3 and chapter 3.5.4 ). comp dsat fixed vref voltage divider dsat _sup _ active 5v class a generation logic vcc2 desat clamping _active gnd2 eicedriver ? sil threshold selection
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 61 rev. 3.1, 2015-07-30 hardware description the desat function is not active while the output st age is in pwm off state. the blanking time needs to be chosen carefully, since th e desat protection may be de facto inhibited if the pwm on-time is too short compared to the chosen blanking time. the detection threshold can be selected by configuring bit field scfg2 . dsatl . at turn-off, the desat signal is pulled down for the duration of the ttoff plateau time, and extended by the blanking time once the hard tu rn off sequence is initiated. figure 3-2 desat operation note: . in case the desat pin is open, the pull-up resi stance ensures that a desat ev ent is generated at the next pwm turn-on command. desat clamping during turn-off the internal pull-up resi stance may lead to t he unwanted charging of the dc-link capacitance via the desat pin. in order to overcome this, the desat func tion needs to be acti vated by clearing bit scfg . dstcen . when this bit is set, pin desat is internally clamped to gnd2 when a pwm off command is issued by the device. v ton / v toff v ee2 v desat v cc2 0v time time t ttoff v cc2 ~ ~ ~ ~ t blank t blank
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 62 rev. 3.1, 2015-07-30 hardware description figure 3-3 desat operation wi th desat clamping enabled 3.2.2 overcurrent protection the integrated over current protection (ocp) functionality is summarized in table 3-3 : the integrated over current protection (ocp) function aims at protecting the igbt in case of overcurrent and short-circuit conditions. the voltage drop over a sense resistor lo cated on the auxiliary emit ter path of the igbt is monitored via the ocp while the device issues a pwm on command. the voltage at pin ocp is externally filtered by an (optional) rc filter and compared (using several in ternal voltage comparators) to the internal reference thresholds v ocpd1 and v ocpd2 (see figure 3-4 ). the result of these comparisons is available by reading bits sstat2 . ocpc1 and sstat2 . ocpc2 . note: bits sstat2 . ocpc1 and ocpc2 are blanked by the selected blanking time. at the beginning of a turn-on sequence, the internal evaluation of the voltage at pin ocp is inhibited for the duration the blanking time defined by register socp . once the blanking time has elapsed, the voltage at pin ocp is compared to an internal reference voltage. table 3-3 ocp function overview parameter short description function monitoring of the voltage drop over an external resistor located on the auxiliary emitter path of the igbt. periodicity continuous while device issues a pwm on command. action in case of failure event 1. emergency (safe) turn-off sequence. 2. error flag ser . ocper is set. 3. assertion of signal nflta . programmability no in-system testability yes (see chapter 3.5.6 ). v ton / v toff v ee2 v desat v cc2 0v time time t ttoff v cc2 ~ ~ ~ ~ t blank
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 63 rev. 3.1, 2015-07-30 hardware description in case the measured voltage at pin ocp is higher than the internal threshold v ocpd1 , an emergency (safe) turn- off sequence is initiated, bit ser . ocper is set and a fault notification is issued on pin nflta (in case of an opm transition the state machine - see chapter 2.4.7 ). in case the measured voltage at pin ocp is higher than the internal threshold v ocpd2 , the sticky bit sstat . ocpcd is set. the allows to verify during application run time the signal integrity of the sense path. the ocp function is not active while the output stage is in pwm off state. figure 3-4 ocp function: principle of operation note: both desat and ocp protection me chanisms can be used simultaneously. note: in case the ocp pin is open, the pull-up resistance en sures that an ocp event is generated. ocp comp1 comp2 300 mv 50 mv class a generation ocp_ sup _active logic w ar ning bit ocpg ocpg 5v 5v ocpg rsense gnd2 eicedriver ? sil
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 64 rev. 3.1, 2015-07-30 hardware description 3.2.3 external enable the external enable functionality is summarized in table 3-4 : the functionality of the signal at pin en/fen is given in chapter 2.4.8 . in case of a valid-to-invalid signal transition, an error is detected. in this case, an emergency (regular) turn-off sequence is initiated, bit per . ener is set and a fault notification is issued on pin nflta (in case of an opm transit ion the state machine - see chapter 2.4.7 ). the current validity state of the signal at pin en/fen can be read on bit pstat2 . enval . this function can be tested by generating an invalid signal on pin en/fen and verifying that the actions done by the device correspond to the expected behavior. table 3-4 external enable function overview parameter short description function external enable. periodicity invalid signal on en/fen pin. action in case of failure event 1. emergency (regular) turn-off sequence. 2. error flag per . ener is set. 3. assertion of signal nflta . programmability no. in-system testability yes.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 65 rev. 3.1, 2015-07-30 hardware description 3.2.4 output stage monitoring the output stage monitoring functionality is summarized in table 3-5 : signals ton and toff are normally connected to an external booster ( figure 5-1 ). in case the inputs of the booster can not be driven (e.g. short circuit), the result ing high currents may lead to the destruction of the 1EDI2002AS and / or of the booster. this failure case is avoided thanks to the output stage monitoring function. when levels at ton and toff differ from the expected levels, th e output stage is tristated and bit sstat . hz is set. a transition of bit sstat . hz from 0 b to 1 b generates an event class a: bit sctrl . ostc and error flag ser . oster are set, signal nflta is asserted (see chapter 2.4.7 ). the monitoring is continuous, but is inhibited for the inhibition time t osm after commutation. at turn-on, time t osm is counted from the beginning of the turn-on sequence. at turn-off, time t osm is counted from the moment where the hard switching action takes place (after the ttoff plateau). signal ton is compared against v osmon . signal toff is compared against v osmof. note: bit sctrl . ostc is cleared either by setting bit pctrl . clrs or by a falling edge of signal osd . in opm5 and opm6, output stage monitoring for ton is disabled. output stage monitoring is disabled when the device is already in tristate (for example, when pin osd is at high level). the output stage returns from tr istate to normal conditions when bit sstat . hz is cleared. clearing bit sstat . hz reactivates the osm (after the duration of the blanking time). note: the osm can be permanently disabled by setting bit scfg . osmd , for both ton and toff . the osm can be tested on system level by (for example) pulling the igbt gate signal high while the device issues a pwm low command. this can be done for example in combination with the asc function of infineon?s 1ebn100xae ?eicedriver? boost? booste r stage. it can then be verified that the reaction of the device corresponds to the expected behavior. table 3-5 output stage monitoring overview parameter short description function monitoring of signals ton and toff . periodicity continuous. action in case of failure event 1. tristate output stage (bit sstat . hz set) 2. bit sctrl . ostc and error flag ser . oster are set. 3. assertion of signal nflta . programmability yes (can be disabled). in-system testability yes.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 66 rev. 3.1, 2015-07-30 hardware description 3.3 protection functions: category b 3.3.1 power supply voltage monitoring the power supply voltage monitoring functionality is summarized in table 3-6 : in order to ensure a correct switching of the igbt, the device supports an undervoltage lockout (uvlo) function for v cc1 , v cc2 , v ee2 , and an overvoltage lockout (ovlo) function for v cc2 and v ee2 ( figure 3-5 ). figure 3-5 power supply supervision function table 3-6 power supply voltage monitoring overview parameter short description function monitoring of v cc1 , v cc2 , v ee2 . periodicity continuous. action in case of failure event 1. emergency (regular) turn-off sequence. 2. error flag per . rst1 (uvlo1) or ser . uvlo2er or ovlo2er or uvlo3er or ovlo3er ) is set. 3. assertion of signal nrst/rdy (uvlo1 only) or nfltb . programmability yes (ovlo3 only). in-system testability yes (see chapter 3.5.8 ). uvlo3 ovlo3 uvlo2 ovlo2 uvlo1 0v v uvlo1l v uvlo 1h v uvlo2l v uvlo 2h v ovlo 2l v ovlo 2h v uvlo3l v uvlo 3h v ovlo 3l v ovlo 3h valid v cc2 range to enable the device valid v cc2 operating range valid v ee 2 operating range valid v ee2 range to enable the device valid v cc1 operating range valid v cc1 range to enable the device
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 67 rev. 3.1, 2015-07-30 hardware description the v cc1 voltage is compared (using an internal voltage comp arator) to an internal reference threshold. if the power supply voltage v cc1 of the primary chip drops below v uvlo1l , an error is detected. in this case, an emergency (regular) turn-off sequence is initiated and signal nrst/rdy goes low. in case v cc1 reaches afterwards a level higher than v uvlo1h , then the error condition is removed and signal nrst/rdy is deasserted. besides, bit per . rst1 is set. the v cc2 voltage is compared (using an internal voltage comp arator) to an internal reference threshold. if the power supply voltage v cc2 of the secondary chip drops below v uvlo2l , an error is detected. in this case, an emergency (regular) turn-off sequence is initiated, bit ser . uvlo2er is set and signal nfltb is activated (in case of an opm transition the state machine - see chapter 2.4.7 ). in case v cc2 reaches afterwards a level higher than v uvlo2h , then the error condition is removed and the device can be reenabled. the v cc2 voltage is compared (using an internal voltage comp arator) to an internal reference threshold. if the power supply voltage v cc2 of the secondary chip goes above v ovlo2h , an error is detected. in this case, an emergency (regular) turn-off sequence is initiated, bit ser . ovlo2er is set and signal nfltb is activated (in case of an opm transition the state machine - see chapter 2.4.7 ). in case v cc2 reaches afterwards a level below v ovlo2l , then the error condition is removed and the device can be reenabled. the v ee2 voltage is compared (using an internal voltage co mparator) to an internal reference threshold. if the power supply voltage v ee2 of the secondary chip drops below v uvlo3l an error is detected. in this case, an emergency (regular) turn-off sequence is initiated, bit ser . uvlo3er is set and signal nfltb is activated (in case of an opm transition the state machine - see chapter 2.4.7 ). in case v ee2 reaches afterwards a level higher than v uvlo3h , then the error condition is removed and the device can be reenabled. the v ee2 voltage is compared (using an internal voltage co mparator) to an internal reference threshold. if the power supply voltage v ee2 of the secondary chip goes above v ovlo3h , an error is detected. in this case, if bit scfg2 . ovlo3d is set, an emergency (regular) tu rn-off sequence is initiated, bit ser . ovlo3er is set and signal nfltb is activated (in case of an op m transition the state machine - see chapter 2.4.7 ). in case v ee2 reaches afterwards a level below v ovlo3l , then the error condition is removed and the device can be reenabled. in case an error is detected while bit scfg2 . ovlo3d is cleared, no emergency turn-off sequence is initiated, and nfltb is not activated. however, bit is ser . ovlo3er set. the current status of the error detection of ovlo2, uvlo3 and ovlo3 mechanism is available by reading bit sstat2 . uvlo2m , ovlo2m , uvlo3m or ovlo3m respectively. note: in case v cc2 goes below the voltage v rst2 , the secondary chip is kept in reset state. 3.3.2 internal supervision the internal supervision functionality is summarized in table 3-7 : the primary and secondary chips are equipped with internal verification mechanisms ensuring that the key functions of the device are operatin g correctly. the internal blocks which are supervised are listed below: ? lifesign watchdog: mutual verification of the re sponse of both chips (both primary and secondary). ? oscillators (both prim ary and secondary, including op en / short detection on signals iref1 and iref2 ). table 3-7 system supervision overview parameter short description function monitoring of the key in ternal functions of the chip. periodicity continuous. action in case of failure event see below programmability no. in-system testability no.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 68 rev. 3.1, 2015-07-30 hardware description ? memory error (both primary and secondary). 3.3.2.1 lifesign watchdog the primary and the secondary chips monitor each other by the mean of a lifesign signal. the periodicity of the lifesign is typically t ls . each chip expects a lifesign from its counte rpart within a given time window. in case two consecutive lifesign erro rs are detected by a chip, an event class b is generated. depending on which side has detected the error, either bit per . cer1 or ser . cer2 is set. note: bits per . cer1 and ser . cer2 indicate a loss of communication even t. the current status of the internal communication is indicated by bit pstat . srdy . 3.3.2.2 oscillator monitoring the main oscillators on th e primary and on the seco ndary side are monitored continuously. two distinct mechanisms are used for this purpose: ? lifesign watchdog allows to detect significant devi ations from the nominal frequency (both primary and secondary, see above). ? open / short detection on pin iref1 . ? open detection on pin iref2 . in case a failure is detected on pin iref1 , the primary chip is kept in reset state for the duration of the failure and signal nrst/rdy is asserted, this leads to the detection of a lifesign error by the secondary chip, generating thus an event class b. in case a failure is detected on pin iref2 , an emergency (regular) turn-off sequence is initiated. the secondary chip is kept in reset state for the duration of the failure. th is leads to the detection of a lifesign error by the primary chip, generating thus an event class b. 3.3.2.3 memory supervision the configuration parameters of the device, stored in th e registers, are protected with a parity bit protection mechanism. both primary and secondary chips are protected (refer to chapter 4 ). in case a failure is detected on the primary ch ip, it is kept in reset state, and both signal nrst/rdy and nfltb are asserted. the secondary side initiates an emergency (regular) turn-off sequence. in case a memory failure is detected by the second ary chip, an emergency (regular) turn-off sequence is initiated. the secondary chip is kept in reset state for the duration of the failure. this leads to the detection of a lifesign error by the primary chip, generating thus an event class b.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 69 rev. 3.1, 2015-07-30 hardware description 3.4 protection functions: category c 3.4.1 shoot through protection function the shoot through protection (stp) functionality is summarized in table 3-8 : with the implemented stp function, a low-side (resp. high-si de) device is able to moni tor the status of its high- side (resp. low-side) counterpart. the input pin instp provides an input for the pwm signal of the driver?s counterpart ( figure 3-6 ). figure 3-6 shoot through protection: principle of operation in case one of the driver is in on state, the driver?s counterpart pwm input is inhibited, preventing it to turn-on (see chapter 2.4.3 ). a minimum dead time is defined by hardware . this dead time is programmable via bit field pcfg2 . stpdel . conceptually, the stp aims at providing an addi tional ?line of defense? for the system in case erroneous pwm commands are issued by the primary logic. in normal operation, dead time management shall be performed at the microcontroller level. in case a pwm on command is received on pin inp during the inhibition time, a fa ilure event is detected. in this case, the high level at pin inp is ignored and bit per . stper is set. table 3-8 stp overview parameter short description function prevents both high-side and low-side switches to be activated simultaneously. periodicity continuous. action in case of failure event 1. the signal at pin inp is inhibited. 2. error flag per . stper is set. programmability yes (dead time). in-system testability yes. hs ls driver hs logic pwm_hs inp pwm_ls instp l o g i c driver ls inp l o g i c out out instp
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 70 rev. 3.1, 2015-07-30 hardware description note: internal filter ensures that stper is not set for glitches smaller than approximately 50ns. the stp can be tested by applying non valid instp and inp and by checking bit pstat2 . stp . the stp can not be disabled. however, setting pin instp to v gnd1 deactivates de fa cto the function. 3.4.2 gate monitoring the gate monitoring functi onality is summarized in table 3-9 : the goal of this function is to allo w a plausibility check on the igbt ga te voltage signal waveform during a switching sequence, for example in order to tr ack degradations of the igbt gate resistances. the gate monitoring consists in two functi ons: gate timeout and gate timing capture. gate timeout the gate timeout mechanism is active for both turn-on and turn-off sequence. at the beginning of a turn-on sequence, an internal 8-bit timer (in the clock domain osc2) is cleared and starts counting up. when the gate voltage reaches v gate2 , the timer stops. in case the timer overflows, flag per . ger is set. a similar mechanism is initiated at every tu rn-off sequence (regular or safe). when a hard transition occurs, an internal timer is cleared starts counting up . when the gate voltage reaches the value v gate1 , the timer stops. in case the timer overflows, flag per . ger is set. the gate timeout mechanism is a lways active, except in opm5 and opm6. in opm5 and opm6, the gate timeout mechanism is disabled during turn-on sequenc es. it works however normally for turn-off sequences gate timing capture this function is armed when an spi command sets bit pctrl . gtct . this sets both bits sgm1 . gtct1 and sgm2 . gtct2 which indicates that the function is armed. at th e next turn-on, respectively turn-off, sequence, a timing measurement is performed. at the beginning of a turn-on sequence, bit field sgm2 . vtom2 is cleared and the device starts incrementing an internal counter (in the clock domain of ssosc2). when signal gate reaches voltage v gate2 , the value of the timer is stored in bit field sgm2 . vtom2 and bit sgm2 . gtct2 is cleared. in case the timer overflows, value ff h is stored. similarly, at the hard transition of a turn-off sequence, bit field sgm1 . vtom1 is cleared and the device starts incrementing an internal counter (in the clock domain of ssosc2). when signal gate reaches voltage v gate1 , the value of the timer is stored in bit field sgm1 . vtom1 and bit sgm1 . gtct1 is cleared. in case the timer overflows, value ff h is stored. table 3-9 gate monitoring overview parameter short description function monitors the waveform at pin gate . periodicity timeout detection at every pwm command transition. exact timing measurement on request. action in case of failure event flag per . ger is set. programmability no in-system testability yes
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 71 rev. 3.1, 2015-07-30 hardware description figure 3-7 gate monitoring function: timing definition the gate monitoring can be tested on system leve l by (for example) pulling the ig bt gate signal high while the device issues a pwm low command. this can be done fo r example in combination with the asc function of infineon?s 1ebn100xae ?eicedriver? boost? booster stage. it can then be verified that the reaction of the device corresponds to the expected behavior. 3.4.3 temperature monitoring the temperature monitoring functionality is summarized in table 3-10 : the device is equipped with an internal temperature sens or. in case the value measured by the internal sensor temperature exceeds a given threshold, bit per . oter is set. 3.4.4 spi error detection the spi error detection mec hanisms are summarized in table 3-11 : table 3-10 temperature monitoring overview parameter short description function warning in case of over-temperature. periodicity continuous. action in case of failure event flag per . oter is set. programmability no in-system testability no table 3-11 spi error detection overview parameter short description function non valid spi command detection and notification. periodicity continuous. action in case of failure event flag per . spier is set. v tom2 time ~ ~ v gate1 v gate2 v tom1 v gate
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 72 rev. 3.1, 2015-07-30 hardware description for more details, see chapter 2.4.4.4 . the spi error detection mechanism can be tested by insert ing on purpose a dedicated error and by verifying that the device?s reaction is conform to specification. 3.4.5 active shor t circuit support the active short circuit support function is summarized in table 3-12 : this feature is aimed at being used in combination with a booster device suppo rting a direct turn-on input (pin asc, see figure 3-8 ). any time the voltage v cc2 goes below threshold v uvlo2l ,or the internal digital voltage supply is not valid, the open drain pin nuv2 drives a low level for the duration of the event. figure 3-8 asc strategy support the nuv2 pin functionality can be tested on system level by creating the conditions of its activation and verifying that the reaction of the device co rresponds to the expected behavior. programmability yes (par ity can be disabled). in-system testability yes. table 3-12 active short circuit support overview parameter short description function notification in case v cc2 is below the uvlo2 threshold or internal digital supply not valid. periodicity continuous. action in case of failure event signal nuv2 activated. programmability no. in-system testability yes. table 3-11 spi error detection overview (cont?d) parameter short description eiceboost eicesil vcc2 monitor gnd2 gnd2 hv logic asc w eak pull - down nuv2 asc _out
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 73 rev. 3.1, 2015-07-30 hardware description 3.4.6 igbt state monitoring the igbt state monitoring mechanism is summarized in table 3-13 : at every pwm command signa l transition, once the desat blanking time is elapsed, the volt age measured at pin desat is compared with the internal threshold and the result is forwarded to pin dout . that way, the primary logic can compare the igbt state (on / off) with the issues pwm command. the current voltage on pin dout is accessible via spi by reading bit ppin . doutl . pin dout can be activated or deactivated (tristate) via bit pcfg2 . doen1 . besides, bit scfg2 . ismen need to be set as well. in order to be functional, the desat clamping shall be disabled (bit scfg . dstcen cleared). table 3-13 igbt state monitoring overview parameter short description function provides the result of the desat comparison logic to pin dout . periodicity continuous. action in case of failure event none. programmability yes (function can be disabled). in-system testability yes.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 74 rev. 3.1, 2015-07-30 hardware description 3.5 protection functions: category d 3.5.1 operation in verificatio n mode and weak active mode verification mode and weak active mode are used to start intrusive test f unctions on device and system level, in order to verify during life time safety relevant function s. the following functions are supported in verification and weak active mode: ? weak turn-on ? desat supervision level 1 ? desat supervision level 2 ? desat supervision level 3 ? ocp supervision level 1 ? ocp supervision level 3 ? uvlox and ovlox supervision level 1 ? internal clock supervision ? dio supervision ? timing calibration feature intrusive test functions can only be started once a co rrect sequence of spi commands has been received after reset. the implementation of the device ensures that no intrusive function can be started when the device is normally active. a time-out function ensures that th e device quits opm5 or opm6 to opm1 after a hardware defined time. the verification functions are triggered by se tting the corresponding bit fields in registers pscr or sscr in opm2. the settings are then activated in opm5. only one verification function should be activated at the time. in opm5 and opm6, gate moni toring for high level and output stage monitoring on pin ton are disabled note: in opm5 and opm6 mode, it is recommended to have bit field ssttof . stval programmed to 0 h . 3.5.2 weak turn on the weak-turn on (wto) corresponds to the operation when mode opm6 is active. the purpose of the weak turn-on functiona lity is to perform a ?probe? test of the igbt, by switching it on with a reduced gate voltage, in order to limit the current through it in case of overcu rrent conditions. this allows to avoid high currents when the system has no memory of the previous state. in mode opm6, when the driver initiates a turn-on se quence after the reception of a pwm command, the on voltage at signal ton is defined by bit field sctrl . gpons . figure 3-9 shows an idealized weak turn-on sequence. the device allows for external booster voltag e compensation at the igbt gate. when bit scfg2 . vbec is cleared, the voltage at ton at the plateau corresponds to the programmed value. when bit scfg2 . vbec is set, an additional v be (base emitter junction voltage of an internal pn diode) is substracted to the programmed voltage at ton in order to comp ensate for the v be of an external booster. note: when using wto, it is recommended to have the sele cted ttoff (if active) plateau at a smaller voltage than the wto voltage.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 75 rev. 3.1, 2015-07-30 hardware description figure 3-9 idealized weak turn-on sequence v gate v ton v ee2 v ee2 v toff v cc2 v ee2 turn-on event t pdon t ttoff time time time 5v gnd2 v daclp time ~ ~ turn-off event t doff t ttoff ~ ~ v cc2 v gponx ~ ~ ~ ~ t acl v gate1 reduced level
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 76 rev. 3.1, 2015-07-30 hardware description 3.5.3 desat supervision level 1 the desat supervision level 1 f unctionality is summarized in table 3-14 : the purpose of the desat supervision leve l 1 function is to verify that the desat feature is o perational over the whole life time of the applicatio n. since the desat supe rvision is intrusive, it is in tended to be executed when the device is in mode opm5 and opm6 (e.g. after power-up during the initialization phase). this mechanism aims at generating artificially a desat error, verifying that it is recognized by the device and that an error notification is correctly issued to the primary logic. when this function is triggered, the driver enters a s pecial mode where the signal input of the comparator is internally pulled up above the threshold voltage (see figure 3-1 ). the desat function wo rks normally otherwise. when the device ent ers opm6 and turns on, after the blanking time has elapse d, a desat error is generated, with the corresponding actions being triggered by the device. the inp signal is issued at the output stage (weak turn-on). 3.5.4 desat supervision level 2 the desat supervision level 2 f unctionality is summarized in table 3-15 : the purpose of the desat supervision leve l 2 function is to verify that the desat feature is o perational over the whole life time of the applicatio n. since the desat supe rvision is intrusive, it is in tended to be executed when the device is in mode opm5 and opm6 (e.g. after power-up during the initialization phase). this mechanism aims at generating artificially a desat error, verifying that it is recognized by the device and that an error notification is correctly issued to the primary logic. when this function is triggered, the driver enters a special mode where, as soon as the device is in opm6 and a pwm turn-on command is received, no action is executed on the output st age. however, the desat logic works normally. it means that after the blan king time has elapsed, the voltage on pin desat should exceed the desat threshold level, leading to a desat error, with the corres ponding actions being tr iggered by the driver. the inp signal is not issued at the output stage. table 3-14 desat supervision level 1 overview parameter short description function supervision of the desat functionality. periodicity on request. action in case of failure event n.a. programmability no in-system testability no table 3-15 desat supervision level 2 overview parameter short description function supervision of the desat functionality. periodicity on request. action in case of failure event n.a. programmability no in-system testability no
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 77 rev. 3.1, 2015-07-30 hardware description 3.5.5 desat supervision level 3 the desat supervision level 3 f unctionality is summarized in table 3-16 : the purpose of the desat supervision leve l 3 function is to verify that the desat feature is o perational over the whole life time of the applicatio n. since the desat supe rvision is intrusive, it is in tended to be executed when the device is in mode opm5 and opm6 (e.g. after power-up during the initialization phase). this mechanism aims at generating artificially a desat error, verifying that it is recognized by the device and that an error notification is correctly issued to the primary logic. when this function is triggered, the driver enters a s pecial mode where the signal input of the comparator is internally pulled up above the threshold voltage (see figure 3-1 ). when the device ente rs opm6, independently from the pwm signal, a desat error is generated, with t he corresponding acti ons being triggere d by the device. the inp signal is not issued at the output stage. note: when using desat superv ision level 3, bit field ssttof . stval must be programmed to 0 h 3.5.6 ocp superv ision level 1 the ocp supervision functi onality is summarized in table 3-17 : the purpose of the ocp supervision level 1 function is to verify that the ocp feature is operati onal over the whole life time of the application. since the ocp supervision is intrusive, it is in tended to be executed when the device is in mode opm5 and opm6 (e.g. after power-up during th e initialization phase). the ma in goal of this mechanism is to generate artificially an ocp error, to verify that it is recognized by the driver and that an error notification is correctly issued to the primary logic. when this function is triggered, the driver enters a spec ial mode where here the signal input of both comparators is internally pulled up above thei r respective threshold voltages (see figure 3-4 ). the ocp function works normally otherwise. when the device enters opm6 and turns on, after the blanking time has elapsed, an ocp error is generated, with the correspondin g actions being triggered by the device. the inp signal is issued at the output stage (weak turn-on). table 3-16 desat supervision level 3 overview parameter short description function supervision of the desat functionality. periodicity on request. action in case of failure event n.a. programmability no in-system testability no table 3-17 ocp supervision level 1 overview parameter short description function supervision of the ocp functionality. periodicity on request. action in case of failure event n.a. programmability no in-system testability no
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 78 rev. 3.1, 2015-07-30 hardware description 3.5.7 ocp superv ision level 3 the ocp supervision functi onality is summarized in table 3-18 : the purpose of the ocp supervision level 3 function is to verify that the ocp feature is operati onal over the whole life time of the application. since the ocp supervision is intrusive, it is in tended to be executed when the device is in mode opm5 and opm6 (e.g. after power-up during th e initialization phase). the ma in goal of this mechanism is to generate artificially an ocp error, to verify that it is recognized by the driver and that an error notification is correctly issued to the primary logic. when this function is triggered, the driver enters a spec ial mode where here the signal input of both comparators is internally pulled up above their respective threshold voltages (see figure 3-4 ). when the device enters opm6, independently from the pwm command, an ocp error is generated, with the corr esponding actions being triggered by the device. the inp signal is not issued at the output stage. note: when using ocp supervision level 3, bit field ssttof . stval must be programmed to 0 h 3.5.8 power supply m onitoring supervision the power supply monitoring supervision monitoring functionality is summarized in table 3-19 : the purpose of this supervision functi on is to verify that the power supply monitoring functions (uvlo2, ovlo2, uvlo3, ovlo3) are operational over the whole life time of th e application. since this supe rvision is intrusive, it is intended to be executed when the device is in mode opm5 (e.g. after power-up during the initialization phase). the main goal of this mechanism is to generate artificially a powe r supply monitoring error, in order to verify that it is recognized by the driver and that an error no tification is correctly issued to the primary logic. when this function is triggered, the supervision mech anism of the power supply addressed by the command is activated. the internal threshold of the comparator delivers a ?dummy? error, with the corresponding actions being triggered by the driver. the supervision of uvlo1 is not supported by the device. table 3-18 ocp supervision level 3 overview parameter short description function supervision of the ocp functionality. periodicity on request. action in case of failure event n.a. programmability no in-system testability no table 3-19 power supply monitoring supervision overview parameter short description function supervision of the power supply monitoring mechanisms. periodicity on request. action in case of event n.a. programmability no in-system testability no
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 79 rev. 3.1, 2015-07-30 hardware description 3.5.9 internal clock supervision the primary clock supervision fu nctionality is summarized in table 3-20 : the clock supervision function consists on th e primary clock supervision and the tcf feature. primary clock supervision the purpose of this supervision function is to verify th e frequency deviation of the primary clock. this function works in such a way that the pwm input signal is used to start and stop a counter clocked by osc1. the function is activated when the device is in opm5 or opm6. the co unter is incremented for the duration of the high level at pin inp . at a high-to-low transition at pin inp, the counter is stopped, and its content is transferred to bit field pcs . cs1 . a plausibility check can ther efore be made by the logi c. in case of a long inp pulse, the counter does not overflow but stays at the maximum value until cleared. pcs . cs1 is cleared by setting bit pctrl . clrp . the inp signal is not issued at the output stage. note: osc2 is indirectly monitored by the life sign mechanism. timing calibration feature the purpose of this supervisi on function is to me asure the frequency of oscillato r ssoc2. the pwm input signal is used to start and stop a counter clocked by ssosc2. the f unction is activated when the device is in opm6 (only). the counter is incremented for the duration of the high level at pin inp . at a high-to-low transition at pin inp, the counter is stopped, and its content is transferred to bit field scs . cs2 . a plausibility ch eck can therefore be made by the logic. in case of a long inp pulse, the counter does not overflow but stays at the maximum value until cleared. scs . cs2 is cleared by a reset event only. the inp signal is not issued at the output stage. 3.5.10 dio supervision the igbt state monitoring mechanisms summarized in table 3-13 : table 3-20 primary cloc k supervision overview parameter short description function supervision of the frequency of osc1 and ssosc2. periodicity on request. action in case of event n.a. programmability no in-system testability no table 3-21 dio supervision overview parameter short description function supervision of the digital channel. periodicity on request. action in case of failure event none. programmability no. in-system testability no.
eicedriver ? sil 1EDI2002AS protection and diagnostics datasheet 80 rev. 3.1, 2015-07-30 hardware description the purpose of this supervision function is to verify the digital channel functionality. pin dio1 shall be configured as an output. the following is valid for opm5 and opm6. this function works on such a way that the signal at pin inp is forwarded internally to pin dio1 , allowing the detection of short circuits on this signal. the inp signal is in this case not forwarded to the secondary chip.
eicedriver ? sil 1EDI2002AS register description datasheet 81 rev. 3.1, 2015-07-30 hardware description 4 register description this chapter describes the internal registers of the device. table 4-1 provides an overview of the implemented registers. the abbreviations shown in table 4-2 are used in the whole section. table 4-1 register overview register short name register long name offset address wakeup value reset value register description , primary register description pid primary id register 00 h n.a. xxxx h pstat primary status register 01 h n.a. 087d h pstat2 primary second status register 02 h n.a. 0010 h per primary error register 03 h n.a. 1c00 h pcfg primary configuration register 04 h n.a. 0004 h pcfg2 primary second configuration register 05 h n.a. 0045 h pctrl primary control register 06 h n.a. 0001 h pctrl2 primary second control register 07 h n.a. 003d h pscr primary supervision function control register 08 h n.a. 0001 h prw primary read/write register 09 h n.a. 0001 h ppin primary pin status register 0a h n.a. xxxx h pcs primary clock supervision register 0b h n.a. 0001 h register description , secondary registers description sid secondary id register 10 h n.a. xxxx h sstat secondary status register 11 h n.a. 0001 h sstat2 secondary second status register 12 h n.a. xxxx h ser secondary error register 13 h n.a. 8011 h scfg secondary configuration register 14 h n.a. 0190 h scfg2 secondary second configuration register 15 h n.a. 0001 h sctrl secondary control register 16 h n.a. 00f1 h sscr secondary supervision function control register 17 h n.a. 0001 h sdesat secondary desat blanking time register 18 h n.a. 2000 h socp secondary ocp blanking time register 19 h n.a. 0001 h srttof secondary regular ttoff configuration register 1a h n.a. 0001 h ssttof secondary safe ttoff configuration register 1b h n.a. 2000 h sgm1 secondary first gate monitoring register 1c h n.a. ff01 h sgm2 secondary second gate monitoring register 1d h n.a. ff01 h
eicedriver ? sil 1EDI2002AS register description datasheet 82 rev. 3.1, 2015-07-30 hardware description the registers are addressed wordwise. saclt secondary active clamping configuration register 1e h n.a. 2600 h scs secondary clock supervision register 1f h n.a. 0001 h table 4-2 bit access terminology mode symbol description basic access types read/write rw this bit or bit field can be written or read. read r this bit or bit field is read only. write w this bit or bit field is write only (read as 0 h ). read/write hardware affected rwh as rw, but bit or bit field can also be modified by hardware. read hardware affected rh as r, but bit or bit field ca n also be modified by hardware. sticky s bits with this attribute are ?sticky? in one direction. if their reset value is once overwritten they can be switched again into their reset state only by a reset operation. software and internal logic (except reset- like functions) cannot switch this ty pe of bit into its reset state by writing directly the register. the sticky attribute can be combined to other functions (e.g. ?rh?). reserved / not implemented 0 bit fields named ?0? indicate not implemented functions. they have the following behavior: ? reading these bit fields returns 0 h . ? writing these bit fields has no effect. these bit fields are reserved. when writing, software should always set such bit fields to 0 h in order to pr eserve compatib ility with future products. reserved / not defined res certain bit fields or bit combinations in a bit field can be marked as ?reserved?, indicating that the behavior of the device is undefined for that combination of bits. setting t he register to such an undefined value may lead to unpredictable resu lts. when writing, software must always set such bit fi elds to legal values. table 4-1 register overview (cont?d) register short name register long name offset address wakeup value reset value
eicedriver ? sil 1EDI2002AS register description datasheet 83 rev. 3.1, 2015-07-30 hardware description 4.1 primary regi ster description primary id register this register contains the identification number of the primary chip version. pid offset wakeup value reset value primary id register 00 h n.a. xxxx h field bits type description pvers 15:4 r primary chip identification this bit field defines the vers ion of the primary chip. this bit field is hard-wired: 4a3 h : ad step. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 r pvers 74 r pvers 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 84 rev. 3.1, 2015-07-30 hardware description primary status register this register contains informatio n on the status of the device. pstat offset wakeup value reset value primary status register 01 h n.a. 087d h field bits type description 0 15:12 r reserved read as 0 b . err 11 rh error status this bit is the or combinati on of all bits of register per . 0 b : no error is detected. 1 b : an error is detected. 0 10 r reserved read as 0 b . gpons 9:8 rh gate turn-on plateau level configuration status this bit field indicates the latest turn-on plateau level configuration request (wto, tton) received by the primary side via the spi interface. coding is identical to bit field pctrl . gpon . act 7 rh active state status this bit indicates if the device is in active state (opm4). 0 b : the device is not in active state. 1 b : the device is in active state. srdy 6 rh secondary ready status this bit indicates if the se condary chip is ready for operation. 0 b : secondary chip is not ready. 1 b : secondary chip is ready. gpofs 5:2 rh gate turn-off plateau level configuration status (regular turn-off) this bit field indicates the latest turn-off plateau level configuration request (regular ttoff) received by the primary side via the spi interface. coding is identical to bit field pctrl2 . gpof . 15 8 7 0 15 12 r 0 11 11 rh err 10 10 r 0 98 rh gpons 7 7 rh act 6 6 rh srdy 52 rh gpofs 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 85 rev. 3.1, 2015-07-30 hardware description lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 86 rev. 3.1, 2015-07-30 hardware description primary second status register this register contains informatio n on the status of the device. pstat2 offset wakeup value reset value primary second status register 02 h n.a. 0010 h field bits type description 0 15:12 r reserved read as 0 b . ostc 11 rh output stage tristate control this bit is set in case an osm event. note: this bit is a mirror of bit sctrl . ostc stp 10 rh shoot through protection status this bit is set in case the shoot through protection inhibition time (i.e. would inhibit a pwm rising edge). 0 b : stp inhibition is not active. 1 b : stp inhibition is active. ot 9 rh over temperature status this bit is set in case an overtemperature condition is detected. 0 b : the device is in normal operation. 1 b : the device is in overtemperature condition. note: this bit is a mirror of bit sstat . ot hz 8 rh tristate output stage status this bit is set in case the output stage is in tristate. 0 b : the output stage is in normal operation. 1 b : the output stage is tristated. note: this bit is a mirror of bit sstat . hz 15 8 7 0 15 12 r 0 11 11 rh ostc 10 10 rh stp 9 9 rh ot 8 8 rh hz 75 rh opm 4 4 rhs fltb 3 3 rhs flta 2 2 rh enval 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 87 rev. 3.1, 2015-07-30 hardware description opm 7:5 rh operating mode this bit field indicates which operating mode is active. 000 b : mode opm0 is active. 001 b : mode opm1 is active. 010 b : mode opm2 is active. 011 b : mode opm3 is active. 100 b : mode opm4 is active. 101 b : mode opm5 is active. 110 b : mode opm6 is active. 111 b : reserved. note: this bit field is a mirror of bit field sstat . opm fltb 4 rhs nfltb driver request this bit indicates what output state is driven by the device at pin nfltb . 0 b : nfltb is tristated. 1 b : a low level is issued at nfltb . this bit is sticky. flta 3 rhs nflta driver request this bit indicates what output state is driven by the device at pin nflta . 0 b : nflta is tristated. 1 b : a low level issued at nflta . this bit is sticky. enval 2 rh en/fen valid status this bit indicates if the signal received on pin en/fen is valid. 0 b : a non-valid signal is detected. 1 b : a valid signal is detected. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 88 rev. 3.1, 2015-07-30 hardware description primary error register this register provides information on the error status of the device. per offset wakeup value reset value primary error register 03 h n.a. 1c00 h field bits type description 0 15:13 r reserved read as 0 b . rste1 12 rhs external hard reset primary flag this bit indicates if a reset event has been detected on the primary chip due to the activation of pin nrst/rdy . 0 b : no external hard reset event has been detected. 1 b : an externally hard reset event has been detected. this bit is sticky. rst1 11 rhs reset primary flag this bit indicates if a reset event has been detected on the primary chip. 0 b : no reset event has been detected. 1 b : a reset event has been detected. this bit is sticky. ener 10 rhs en/fen signal invalid flag this bit indicates if an invalid-to-valid transition on signal en/fen has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit pstat2 . enval cleared). 15 8 7 0 15 13 r 0 12 12 rhs rste1 11 11 rhs rst1 10 10 rhs ener 9 9 rhs stper 8 8 rhs spier 7 7 rh vmto 6 6 rh ger 5 5 rh ovlo3er 4 4 rh oter 3 3 rh oster 2 2 rhs cer1 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 89 rev. 3.1, 2015-07-30 hardware description stper 9 rhs shoot through protection error flag this bit indicates if a shoot through protection error event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit pstat2 . stp set). spier 8 rhs spi error flag this indicates if an spi error event has been detected. 0 b : no error event has been detected. 1 b : an error event has been detected. this bit is sticky. vmto 7 rh verif. mode time-out flag this bit indicates if a verifi cation mode time-out event has been detected. 0 b : no time-out event has been detected. 1 b : a time-out event has been detected. note: this bit is a mirror of bit ser . vmto . ger 6 rh gate monitoring error flag this bit indicates if a gate monitoring timer overflow occurred during a switching sequence. 0 b : no error event has been detected. 1 b : an error event has been detected. note: this bit is a mirror of bit ser . ger . ovlo3er 5 rh ovlo3 error flag this bit indicates if an overvoltage lockout event on v ee2 has been detected. 0 b : no error event has been detected. 1 b : an error event has been detected. note: this bit is a mirror of bit ser . ovlo3er . oter 4 rh overtemperature error flag this bit indicates if an overtemperature condition has been detected. 0 b : no event has been detected. 1 b : an event has been detected. note: this bit is a mirror of bit ser . oter . oster 3 rh output stage tristate event flag this bit indicates if the output stage has been tristated. 0 b : no tristate event has been detected. 1 b : a tristate event has been detected. note: this bit is a mirror of bit ser . oster . field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 90 rev. 3.1, 2015-07-30 hardware description cer1 2 rhs communication error primary flag this indicates if a loss of communication event 1) with the secondary chip has been detected by the primary chip. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit pstat2 . srdy cleared). lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 1) this bit is not set after a reset event field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 91 rev. 3.1, 2015-07-30 hardware description primary configuration register this register is used to select the configuration of the device. pcfg offset wakeup value reset value primary configuration register 04 h n.a. 0004 h field bits type description 0 15:6 r reserved read as 0 b . osmaen 5 rw nflta activation on osm event enable bit this bit enables the activation of signal nflta in case of a transition from 0 b to 1 b of bit pstat2 . ostc . 0 b : nflta activation is disabled. 1 b : nflta activation is enabled ostaen 4 rw nflta activation on tristate event enable bit this bit enables the activation of signal nflta in case of a transition from 0 b to 1 b of bit per . oster . 0 b : nflta activation is disabled. 1 b : nflta activation is enabled cfg1 3 rwh advanced primary configuration enable bit this bit enables write accesses to register pcfg2 . 0 b : write access to pcfg2 are discarded. 1 b : write access to pcfg2 are executed normally. this bit is automatically cl eared when mode opm2 is left. paren 2 rw parity enable bit this bit indicates if the spi pa rity error detection is active (reception only). 0 b : parity check is disabled. 1 b : parity check is enabled. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 r 0 76 r 0 5 5 rw osmaen 4 4 rw ostaen 3 3 rwh cfg1 2 2 rw paren 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 92 rev. 3.1, 2015-07-30 hardware description primary second configuration register this register is used to select the configurat ion of the device. it can only be written if bit pcfg . cfg1 is set. pcfg2 offset wakeup value reset value primary second configuration register 05 h n.a. 0045 h field bits type description 0 15:10 r reserved read as 0 b . doen1 9 rw dout output primary enable bit this bit is used to enable the dout signal. 0 b : dout is disabled (and in tristate). 1 b : dout is enabled (output). dio1 8 rw digital channel configuration this bit field determines the direction of pin dio1 . 0 b : dio1 is an input. 1 b : dio1 is an output. fen 7 rw en/fen mode configuration this bit determines the validit y mode of a signal at pin en/fen . 0 b : en mode active. a valid signal is defined as a high level. 1 b : fen mode active. a valid signal is defined as a periodic signal. stpdel 6:2 rw shoot through protection delay configuration this bit field determines the dead time for the shoot- through protection (in number of osc1 clock cycles). 00 h : 0 clock cycle. 01 h : 1 clock cycle. ... 1f h : 31 clock cycles. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. 15 8 7 0 15 10 r 0 9 9 rw doen1 8 8 rw dio1 7 7 rw fen 62 rw stpdel 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 93 rev. 3.1, 2015-07-30 hardware description p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 94 rev. 3.1, 2015-07-30 hardware description primary control register this register is used to contro l the device during run-time. pctrl offset wakeup value reset value primary control register 06 h n.a. 0001 h field bits type description 0 15:7 r reserved read as 0 b . clrs 6 rwh clear secondary request bit this bit is used to clear the sticky bits on the secondary side. 0 b : no action. 1 b : clear sticky bits. this bit is automatically cleared by hardware. clrp 5 rwh clear primary request bit this bit is used to clear the sticky bits on the primary side. 0 b : no action. 1 b : clear sticky bits and deassert signals nflta and nfltb . this bit is automatically cleared by hardware. gtct 4 rwh gate timing capture trigger bit this bit is used to trigger the timing capture mechanism measurements of the gate monitoring function. 0 b : no action. 1 b : timing capture triggered. this bit is automatically cleared by hardware gpon 3:2 rw gate turn-on plateau level configuration this bit field is used to configure the voltage of the plateau during weak turn-o n and two level turn-on. 0 h : v gpon0 selected. 1 h : v gpon1 selected. 2 h : v gpon2 selected. 3 h : reserved (wto) or hard switching (tton). 15 8 7 0 15 r 0 7 7 r 0 6 6 rwh clrs 5 5 rwh clrp 4 4 rwh gtct 32 rw gpon 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 95 rev. 3.1, 2015-07-30 hardware description lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 96 rev. 3.1, 2015-07-30 hardware description primary second control register this register is used to contro l the device during run-time. pctrl2 offset wakeup value reset value primary second control register 07 h n.a. 003d h field bits type description 0 15:6 r reserved read as 0 b . gpof 5:2 rw gate turn-off plateau level configuration (regular turn-off) this bit field is used to configure the two-level turn-off plateau voltage (regular turn-off). 0000 b : v gpof0 selected. 0001 b : v gpof1 selected. ... 1110 b : v gpof14 selected. 1111 b : v gpof15 selected. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 r 0 76 r 0 52 rw gpof 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 97 rev. 3.1, 2015-07-30 hardware description primary supervision function control register this register is used to trigger the verification functions on the primary side. pscr offset wakeup value reset value primary supervision function control register 08 h n.a. 0001 h field bits type description 0 15:4 r reserved read as 0 b . vfs1 3:2 rwh primary verification function selection this bit field is used to activate the primary verification functions. 00 b : no function activated. 01 b : reserved. 10 b : primary clock supervision active. 11 b : dio supervision active. note: the selection defined by this bit field is only effective when the device enters mode opm5. this bit field is automatically cleared when entering opm1. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 r 0 74 r 0 32 rwh vfs1 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 98 rev. 3.1, 2015-07-30 hardware description primary read/write register this register provides a readable and wr itable address space for data integrity te st during runtime. this register is not associated with any hardware functionality. prw offset wakeup value reset value primary read/write register 09 h n.a. 0001 h field bits type description rwval 15:2 rw read/write value this bit field is ?don?t care? for the device. lmi 1 rh last message invalid flag this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message processed correctly. 1 b : previous message not processed. p 0 rh parity bit odd parity bit. 15 8 7 0 15 rw rwval 72 rw rwval 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 99 rev. 3.1, 2015-07-30 hardware description primary pin status register this register provides status informat ion on the i/os of the primary chip. ppin offset wakeup value reset value primary pin status register 0a h n.a. xxxx h field bits type description 0 15:9 r reserved read as 0 b . dio1l 8 rh pin dio1 level this bit indicates the logical level read on pin dio1 . 0 b : low-level is detected. 1 b : high-level is detected. doutl 7 rh pin dout level this bit indicates the logical level read on pin dout . 0 b : low-level is detected. 1 b : high-level is detected. nfltbl 6 rh pin nfltb level this bit indicates the logical level read on pin nfltb . 0 b : low-level is detected. 1 b : high-level is detected. nfltal 5 rh pin nflta level this bit indicates the logical level read on pin nflta . 0 b : low-level is detected. 1 b : high-level is detected. enl 4 rh pin en/fen level this bit indicates the logical level read on pin en/fen . 0 b : low-level is detected. 1 b : high-level is detected. instpl 3 rh pin instp level this bit indicates the logical level read on pin instp . 0 b : low-level is detected. 1 b : high-level is detected. 15 8 7 0 15 9 r 0 8 8 rh dio1l 7 7 rh doutl 6 6 rh nfltbl 5 5 rh nfltal 4 4 rh enl 3 3 rh instpl 2 2 rh inpl 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 100 rev. 3.1, 2015-07-30 hardware description inpl 2 rh pin inp level this bit indicates the logical level read on pin inp . 0 b : low-level is detected. 1 b : high-level is detected. lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 101 rev. 3.1, 2015-07-30 hardware description primary clock supervision register this register shows the result of the primary clock supervision function. pcs offset wakeup value reset value primary clock supervision register 0b h n.a. 0001 h field bits type description cs1 15:8 rh primary clock supervision this bit field is written by hardware by the primary clock supervision function and gives the number of measured osc1 clock cycles. note: this bit field can be cleared by setting bit pctrl . clrp . 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rh cs1 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 102 rev. 3.1, 2015-07-30 hardware description 4.2 secondary registers description secondary id register this register contains the identification number of secondary chip version. sid offset wakeup value reset value secondary id register 10 h n.a. xxxx h field bits type description svers 15:4 r secondary chip identification this bit field defines the ve rsion of the secondary chip. this bit field is hard-wired: 8b2 h : ad step. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 r svers 74 r svers 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 103 rev. 3.1, 2015-07-30 hardware description secondary status register this register contains informatio n on the status of the device. sstat offset wakeup value reset value secondary status register 11 h n.a. 0001 h field bits type description res 15:14 rh reserved this bit field is reserved. ot 13 rh overtemperature status this bit indicates if an overtemperature condition is detected. 0 b : no overtemperature condition is detected. 1 b : overtemperature condition is detected. hz 12 rh output stage status this bit indicates the st ate of the output stage. 0 b : the output stage is operating normally. 1 b : the output stage is tristated. ocpcd 11 rhs ocp current detection flag this bit indicates if the voltage at pin ocp has been above the internal threshold v ocpd2 . 0 b : ocp voltage has not been above internal threshold. 1 b : ocp voltage has been above internal threshold. this bit is sticky. dbg 10 rh debug mode active bit this bit indicates if the debug mode is active. 0 b : debug mode is not active. 1 b : debug mode is active. opm 9:7 rh operating mode this bit field indicates in which operating mode is active. the coding is identical to pstat2 . fltb 6 rh event class b status this bit indicates if the conditions leading to an event class b are detected. 0 b : event conditions are not met. 1 b : event conditions are met. 15 8 7 0 15 14 res 13 13 rh ot 12 12 rh hz 11 11 rhs ocpcd 10 10 rh dbg 9 rh opm 7 7 rh opm 6 6 rh fltb 5 5 rh flta 4 4 rh pwm 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 104 rev. 3.1, 2015-07-30 hardware description flta 5 rh event class a error this bit indicates if the conditions leading to an event class a are detected. 0 b : event conditions are not met. 1 b : event conditions are met. pwm 4 rh pwm command status this bit indicates the status of the pwm command received from the primary side. 0 b : pwm off command is detected. 1 b : pwm on command is detected. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 105 rev. 3.1, 2015-07-30 hardware description secondary second status register this register contains informatio n on the status of the device. sstat2 offset wakeup value reset value secondary second status register 12 h n.a. xxxx h field bits type description dio2l 15 rh dio2 level this bit indicates the level read at pin dio2 . 0 b : dio2 level is low. 1 b : dio2 level is high. daclpl 14 rh daclp level this bit indicates the level read at pin daclp . 0 b : daclp level is low. 1 b : daclp level is high. gc2 13 rh gate second comparator status this bit shows the output of the second comparator of the gate monitoring function. 0 b : gate voltage is below v gate2 . 1 b : gate voltage is above v gate2 . gc1 12 rh gate first comparator status this bit indicates the output of the first comparator of the gate monitoring function. 0 b : gate voltage is below v gate1 . 1 b : gate voltage is above v gate1 . ovlo3m 11 rh ovlo3 comparator status this bit indicates the result of the ovlo3 monitoring function. 0 b : no failure condition is detected. 1 b : a failure condition is detected. uvlo3m 10 rh uvlo3 monitoring result this bit indicates the result of the uvlo3 monitoring function. 0 b : no failure condition is detected. 1 b : a failure condition is detected. 15 8 7 0 15 15 rh dio2l 14 14 rh daclpl 13 13 rh gc2 12 12 rh gc1 11 11 rh ovlo3m 10 10 rh uvlo3m 9 9 rh ovlo2m 8 8 rh uvlo2m 7 7 rh ocpc2 6 6 rh ocpc1 5 5 rh osdl 4 4 rh dsatc 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 106 rev. 3.1, 2015-07-30 hardware description ovlo2m 9 rh ovlo2 monitoring result this bit indicates the result of the ovlo2 monitoring function. 0 b : no failure condition is detected. 1 b : a failure condition is detected. uvlo2m 8 rh uvlo2 monitoring result this bit indicates the result of the uvlo2 monitoring function. 0 b : no failure condition is detected. 1 b : one failure condition is detected. ocpc2 7 rh ocp second comparator result this bit indicates the (blanked) output of the second comparator of the ocp function. 0 b : ocp voltage is below v ocpd2 . 1 b : ocp voltage is above v ocpd2 . ocpc1 6 rh ocp first comparator result this bit indicates the (blanked) output of the first comparator of the ocp function. 0 b : ocp voltage is below v ocpd1 . 1 b : ocp voltage is above v ocpd1 . osdl 5 rh osd level this bit indicates the level read at pin osd . 0 b : osd level is low. 1 b : osd level is high. dsatc 4 rh desat comparator result this bit indicates the output of the comparator of the desat function. 0 b : desat voltage is below v desat . 1 b : desat voltage is above v desat . 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 107 rev. 3.1, 2015-07-30 hardware description secondary error register this register provides information on the error status of the device. ser offset wakeup value reset value secondary error register 13 h n.a. 8011 h field bits type description rst2 15 rhs hard reset secondary flag this bit indicates if a hard reset event has been detected on the secondary chip (due to a v cc2 power-up). 0 b : no hard reset event has been detected. 1 b : a hard reset event has been detected. this bit is sticky. ocper 14 rhs ocp error flag this bit indicates if an ocp event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit sstat2 . ocpc1 set). desater 13 rhs desat error flag this bit indicates if a desat event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. uvlo2er 12 rhs uvlo2 error flag this bit indicates if an undervoltage lockout event (on v cc2 ) has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit sstat2 . uvlo2m set). 15 8 7 0 15 15 rhs rst2 14 14 rhs ocper 13 13 rhs desater 12 12 rhs uvlo2er 11 11 rhs ovlo2er 10 10 rhs uvlo3er 9 9 rhs vmto 8 8 rhs ger 7 7 rhs ovlo3er 6 6 rhs oter 5 5 rhs oster 4 4 rhs cer2 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 108 rev. 3.1, 2015-07-30 hardware description ovlo2er 11 rhs ovlo2 error flag this bit indicates if an overvoltage lockout event (on v cc2 ) has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit sstat2 . ovlo2m set). uvlo3er 10 rhs uvlo3 error flag this bit indicates if an undervoltage lockout event (on v ee2 ) has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit sstat2 . uvlo3m set). vmto 9 rhs verif. mode time-out flag this bit indicates if time-out event in verification mode has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. ger 8 rhs gate monitoring error flag this bit indicates in a gate monitoring error event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. ovlo3er 7 rhs ovlo3 error flag this bit indicates if an overvoltage lockout event (on v ee2 ) has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared while an error condition is active (bit sstat2 . ovlo3m set). oter 6 rhs overtemperature error flag this bit indicates if an overtemperature event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared if bit sstat . ot is set. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 109 rev. 3.1, 2015-07-30 hardware description oster 5 rhs output stage tristate event flag this bit indicates if an output stage tristate event has been detected. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. note: this bit can not be cleared if bit sstat . hz is set. cer2 4 rhs communication error secondary flag this indicates if a loss of communication event with the primary chip has been detected by the secondary chip. 0 b : no event has been detected. 1 b : an event has been detected. this bit is sticky. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 110 rev. 3.1, 2015-07-30 hardware description secondary configuration register this register is used to select the configuration of the device. scfg offset wakeup value reset value secondary configuration register 14 h n.a. 0190 h field bits type description 0 15:11 r reserved read as 0 b . tosen 10 rw verification mode time out duration selection this bit selects the duration of the verification mode time out. 0 b : regular time-out value (typ. 15 ms). 1 b : slow time-out value (typ. 60 ms). psen 9 rw pulse suppressor enable bit this bit enables the internal pulse suppressor. 0 b : pulse suppressor is disabled. 1 b : pulse suppressor is enabled. dstcen 8 rw desat clamping enable bit this bit enables the internal clamping (to gnd2) of the desat pin during pwm off commands. 0 b : desat clamping is disabled. 1 b : desat clamping is enabled. osdad 7 rw osd event class a disable bit this bit disables the generation of an event class a in case of an osd pin tristate event. 0 b : event class a is enabled. 1 b : event class a is disabled. osmd 6 rw output stage monitoring disable bit this bit disables the internal output stage monitoring mechanism. 0 b : osm is working normally. 1 b : osm is disabled. 15 8 7 0 15 11 r 0 10 10 rw tosen 9 9 rw psen 8 8 rw dstcen 7 7 rw osdad 6 6 rw osmd 5 5 rwh cfg2 4 4 rw vbec 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 111 rev. 3.1, 2015-07-30 hardware description cfg2 5 rwh advanced secondary configuration enable bit this bit field enables write accesses to register scfg2 . 0 b : write access to scfg2 are discarded. 1 b : write access to scfg2 are executed normally. this bit is cleared when leaving mode opm2. vbec 4 rw v be compensation this bit enables the v be compensation of the ttoff, tton and wto plateau levels. 0 b : v be compensation disabled. 1 b : v be compensation enabled. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 112 rev. 3.1, 2015-07-30 hardware description secondary second configuration register this register is used to select the configurat ion of the device. it can only be written if bit scfg . cfg2 is set. scfg2 offset wakeup value reset value secondary second configuration register 15 h n.a. 0001 h field bits type description res 15:14 rw reserved this bit field is reserved. it should be written with 0 h . ismen 13 rw igbt state monitoring function enable bit this bit enables the igbt st ate monitoring function on the secondary side. 0 b : functionality is disabled. 1 b : functionality is enabled. ovlo3d 12 rw ovlo3 mode configuration this bit configures the operation of the ovlo3 function. 0 b : ovlo3 events are events class b. 1 b : ovlo3 events are warning events. aclpm 11 rw active clamping mode this bit determines the mode of operation of pin daclp . 0 b : daclp is active for regular and safe turn-off sequences. 1 b : daclp is active only in case of a safe turn-off sequence. dio2 10 rw digital channel configuration this bit field determines the direction of pin dio2 . 0 b : dio2 is an input. 1 b : dio2 is an output. ttond 9:6 rw tton delay configuration this bit field defines the tton delay (in ssosc2 clock cycles). writing 00 h to this field deactivates the tton function. if used, a minimal value of at least a h has to be programmed. 15 8 7 0 15 14 res 13 13 rw ismen 12 12 rw ovlo3d 11 11 rw aclpm 10 10 rw dio2 9 rw ttond 76 rw ttond 54 rw dsatl 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 113 rev. 3.1, 2015-07-30 hardware description dsatl 5:4 rw desat threshold level selection this bit field config ures the threshold level of the desat function. 00 b : threshold v desat0 selected. 01 b : threshold v desat1 selected. 10 b : threshold v desat2 selected. 11 b : threshold v desat3 selected. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 114 rev. 3.1, 2015-07-30 hardware description secondary control register this register is used to contro l the device during run-time. sctrl offset wakeup value reset value secondary control register 16 h n.a. 00f1 h field bits type description 0 15:13 r reserved read as 0 b . ostc 12 rhs output stage tristate control this bit is used by the hardware to control the state of the output stage.this bit is set in case of an osm event. it is cleared by either a falling edge on pin osd or when bit pctrl . clrs is set. clrs 11 rh clear secondary request bit this bit is set by writing pctrl . clrs . 0 10 rh reserved read as 0 b . gpons 9:8 rh gate turn-on plateau level configuration this bit field indicates the current configuration of the plateau level for wto and tton. coding is identical to pctrl . gpon . note: this bit field is a mirror of pstat . gpons . gpofs 7:4 rh gate turn-off plateau level configuration (regular turn-off) this bit field indicates the current configuration of the ttoff plateau level (for regular turn-off). coding is identical to pctrl2 . gpof . note: this bit field is a mirror of pstat . gpofs . 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. 15 8 7 0 15 13 r 0 12 12 rhs ostc 11 11 rh clrs 10 10 rh 0 98 rh gpons 74 rh gpofs 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 115 rev. 3.1, 2015-07-30 hardware description p 0 rh parity bit odd parity bit. field bits type description
eicedriver ? sil 1EDI2002AS register description datasheet 116 rev. 3.1, 2015-07-30 hardware description secondary supervision function control register this register is used to trigger the veri fication functions on the secondary side. sscr offset wakeup value reset value secondary supervision function control register 17 h n.a. 0001 h field bits type description 0 15:8 r reserved read as 0 b . vfs2 7:4 rwh secondary verification function selection this bit field is used to activa te the secondary verification function. 0000 b : no function activated. 0001 b : desat supervisio n level 1 active. 0010 b : desat supervisio n level 2 active. 0011 b : ocp supervision level 1 active. 0100 b : uvlo2 supervision active. 0101 b : ovlo2 supervision active. 0110 b : uvlo3 supervision active. 0111 b : ovlo3 supervision active. 1000 b : tcf function active. 1001 b : desat supervisio n level 3 active. 1010 b : ocp supervision level 3 active. all other bit combinations are reserved. note: the selection defined by this bit field is only effective when the device enters mode opm5. this bit field is automatically cleared when entering opm1. 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 r 0 74 rwh vfs2 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 117 rev. 3.1, 2015-07-30 hardware description secondary desat blanking time register this register configures the blanking time of the desat function. sdesat offset wakeup value reset value secondary desat blanking time register 18 h n.a. 2000 h field bits type description dsatbt 15:8 rw desat blanking time value. this bit field defines the bl anking time of the desat function (in osc2 clock cycles). if the desat function is used, a value of at least a h shall be programmed. 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rw dsatbt 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 118 rev. 3.1, 2015-07-30 hardware description secondary ocp blanking time register this register configures the blan king time of the ocp function. socp offset wakeup value reset value secondary ocp blanking time register 19 h n.a. 0001 h field bits type description ocpbt 15:8 rw ocp blanking time value. this bit field defines the blank ing time of the ocp function (in osc2 clock cycles). writing 0 h to this field deactivates the digital blanking time generation. this field shall not be programmed with values above 2f h . 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rw ocpbt 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 119 rev. 3.1, 2015-07-30 hardware description secondary regular ttoff configuration register this register shows the configuration of the ttoff function for regular turn-off. srttof offset wakeup value reset value secondary regular ttoff configuration register 1a h n.a. 0001 h field bits type description rtval 15:8 rw ttoff delay value (regular turn-off). this bit field defines the ttoff delay for a regular turn- off (in ssosc2 clock cycles). writing 00 h to this field deactivates the ttoff function for regular turn-off. if used, a minimal value of at least 2 h has to be programmed. 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rw rtval 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 120 rev. 3.1, 2015-07-30 hardware description secondary safe ttoff configuration register this register shows the configuration of the ttoff function for safe turn-off. ssttof offset wakeup value reset value secondary safe ttoff configuration register 1b h n.a. 2000 h field bits type description stval 15:8 rw ttoff delay value (safe turn-off). this bit field defines the tto ff delay for a safe turn-off (in osc2 clock cycles). writing 00 h to this field deactivates the ttoff function for regular turn-off. if used, a minimal value of at least a h has to be programmed. note: 1. in opm5 and opm6, it is recommended to have this bit field programmed to 0 h . 2. in opm4, when safe two leve l turn off is used, bit field stval shall be programmed with a higher value than field srttof . rtval . 3. gps 7:4 rw ttoff plateau voltage (safe turn-off) this bit field defines the tto ff plateau voltage for safe turn-off sequences. co ding is identical to pctrl2 . gpof . note: in opm4, bit field gps shall be programmed with a value smaller or equal than field pctrl2 . gpof . 0 3:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rw stval 74 rw gps 32 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 121 rev. 3.1, 2015-07-30 hardware description secondary first gate monitoring register this register captures the value of the count er monitoring during the switching sequence. sgm1 offset wakeup value reset value secondary first gate monitoring register 1c h n.a. ff01 h field bits type description vtom1 15:8 rh turn-off counter value this bit field is used to ca pture the timing of signal gate during turn-off sequences. it is cleared at the beginning of the timing measurement. gtct1 7 rh gate timing capture trigger 1 this bit indicates the stat e of the timing capture mechanism. when it is set, th e mechanism is armed. this bit is cleared at the end of the timing measurement. note: in case a new request occurs while he mechanism is already armed, then this bit is cleared and the mechanism disarmed. 0 6:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rh vtom1 7 7 rh gtct1 62 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 122 rev. 3.1, 2015-07-30 hardware description secondary second gate monitoring register this register captures the value of the count er monitoring during the switching sequence. sgm2 offset wakeup value reset value secondary second gate monitoring register 1d h n.a. ff01 h field bits type description vtom2 15:8 rh turn-on counter value this bit field is used to ca pture the timing of signal gate during turn-on sequences. it is cleared at the beginning of the timing measurement. gtct2 7 rh gate timing capture trigger 2 this bit indicates the stat e of the timing capture mechanism. when it is set, th e mechanism is armed. this bit is cleared at the end of the timing measurement. note: in case a new request occurs while the mechanism is already armed, then this bit is cleared and the mechanism disarmed. 0 6:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rh vtom2 7 7 rh gtct2 62 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 123 rev. 3.1, 2015-07-30 hardware description secondary daclp activation conf iguration register this register defines the activation time of signal daclp . saclt offset wakeup value reset value secondary active clamping configuration register 1e h n.a. 2600 h field bits type description at 15:8 rw activation time this bit field defines the activation time for signal daclp (in ssosc2 clock cycles). 00 h : daclp is at constant high level. 01 h ...09 h : reserved. 0a h ...fe h : daclp activation time. ff h : daclp is at constant low level. 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rw at 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 124 rev. 3.1, 2015-07-30 hardware description secondary clock supervision register this register is for internal purpose only. scs offset wakeup value reset value secondary clock supervision register 1f h n.a. 0001 h field bits type description cs2 15:8 rh secondary clock supervision this bit field is written by hardware by the tcf function and gives the number of meas ured start st op oscillator clock cycles. 0 7:2 r reserved read as 0 b . lmi 1 rh last message invalid notification this bit indicates if the la st received spi message was correctly processed by the device. 0 b : previous message was processed correctly. 1 b : previous message was discarded. p 0 rh parity bit odd parity bit. 15 8 7 0 15 8 rh cs2 72 r 0 1 1 rh lmi 0 0 rh p
eicedriver ? sil 1EDI2002AS register description datasheet 125 rev. 3.1, 2015-07-30 hardware description 4.3 read / write address ranges table 4-3 summarizes which register is accessible with a read command for a given operating mode. table 4-3 read access validity opm1 opm2 opm3 opm4 opm5 opm6 pid x x x x x x pstat x x x x x x pstat2 x x x x x x per x x x x x x pcfg x x x x x x pcfg2 x x x x x x pctrl x x x x x x pctrl2 x x x x x x pscr x x x x x x prw x x x x x x ppin x x x x x x pcs x x x x x x sid x x x x 1) 1) increased latency time x x 1) sstat x x x x 1) x x 1) sstat2 x x x x 1) x x 1) ser x x x x 1) x x 1) scfg x x x x 1) x x 1) scfg2 x x x x 1) x x 1) sctrl x x x x 1) x x 1) sscr x x x x 1) x x 1) sdesat x x x x 1) x x 1) socp x x x x 1) x x 1) srttof x x x x 1) x x 1) ssttof x x x x 1) x x 1) sgm1 x x x x 1) x x 1) sgm2 x x x x 1) x x 1) saclt x x x x 1) x x 1) scs x x x x 1) x x 1)
eicedriver ? sil 1EDI2002AS register description datasheet 126 rev. 3.1, 2015-07-30 hardware description table 4-4 summarizes which register is accessible with a writel command for a given operating mode. table 4-4 write access validity opm1 opm2 opm3 opm4 opm5 opm6 pid pstat pstat2 per pcfg x pcfg2 1) 1) write access only allowed if pcfg . cfg1 is set x pctrl x x x x x x pctrl2 x x x x x x pscr x prw x x x x x x ppin pcs sid sstat sstat2 ser scfg x scfg2 2) 2) write access only allowed if scfg . cfg2 is set x sctrl sscr x sdesat x socp x srttof x ssttof x sgm1 sgm2 saclt x scs
eicedriver ? sil 1EDI2002AS specification datasheet 127 rev. 3.1, 2015-07-30 hardware description 5 specification 5.1 typical application circuit table 5-1 component values parameter symbol values unit note / test condition min. typ. max. decoupling capacitance (between vee2 and gnd2) c d 2 x 0.5 11 - f 10f capacitance next to the power supply source (e.g. flyback converter). 1 f close to the device. it is strongly recommended to have at least two capacitances close to the device (e.g. 2 x 500nf). decoupling capacitance (between vcc2 and gnd2) c d - 11 - f 10f capacitance next to the power supply source (e.g. flyback converter). 1 f close to the device. decoupling capacitance (between vcc1 and gnd1) c d - 11 - f 10f capacitance next to the power supply source (e.g. flyback converter). 1 f close to the device. series resistance r s1 01- k pull-up resistance r pu1 -10-k filter resistance r 1 -1-k filter capacitance c 1 -47-pf reference resistance r ref1 -26.7 1) -k high accuracy, as close as possible to the device reference capacitance c ref1 - 100 - pf as close as possible to the device. pull-up resistance r pu2 -10-k reference resistance r ref2 -23.7-k high accuracy, as close as possible to the device reference capacitance c ref2 - 100 - pf as close as possible to the device. desat filter resistance r desat 13- k depends on required response time. desat filter capacitance c desat - n/a - nf depends on required response time. desat diode d desat - n/a - - hv diode. osd filter resistance r osd -1-k osd filter capacitance c osd -47-pf sense resistance r sense -n/a- depends on igbt specification.
eicedriver ? sil 1EDI2002AS specification datasheet 128 rev. 3.1, 2015-07-30 hardware description ocp filter resistance r ocp -n/a- depends on required response time. ocp filter capacitance c ocp - n/a - nf depends on required response time. ocpg resistance r ocpg 0- 100 daclp filter resistance r daclp -1-k daclp filter capacitance c daclp -470-pf nuv2 filter resistance r 2 -n/a- depends on required response time. nuv2 filter capacitance c 2 --100pf active clamping resistance r acl1 -n/a- depends on application requirements active clamping resistance r acl2 -n/a-k depends on application requirements active clamping capacitance c acli - n/a - nf depends on application requirements tvs diode d tvsacl1, d tvsacl2 - n/a - - depends on application requirements active clamping diode d acl - n/a - - depends on application requirements acli clamping diode d acl2 - n/a - - depends on application requirements vreg capacitance c vreg 1 f as close as possible to the device. gate resistance r gon 0.5 - - gate resistance r goff 0.5 - - gate clamping diode d gcl1 -n/a-- 2) gate clamping diode d gcl2 - n/a - - e.g. schottky diode. 2) gate series resistance r gate 010- optional component. vee2 clamping diode d gcl3 - n/a - - e.g. schottky diode. 2) 1) 26.1 kohm can also be used 2) characteristics of this comp onents are application specific. table 5-1 component values (cont?d) parameter symbol values unit note / test condition min. typ. max.
eicedriver ? sil 1EDI2002AS specification datasheet 129 rev. 3.1, 2015-07-30 hardware description figure 5-1 typical application example note: components marked with (*) are optional. inp instp iref1 ref0 en nrst/rdy nflta nfltb sdi sdo ncs sc lk nuv2 ton toff desat ocp debug osd daclp toni tono toffo r gon r goff r acl1 vee2 vcc2 r des at c des at gnd2 r ocp c ocp r sense l sense (*) acli gate toffi daclp asc gnd2 0 ? vector generation lv ? logic eicedriver boost r 1 ref0 r 1 r 1 gnd1 r pu1 r pu1 r ref1 d des at d acl d tvsacl1 r acl2(*) d acl2 vee2 gnd2 c d \ 8v vcc2 +15v c d vcc1 +5v r 1 r s1 r 1 r 1 gnd1 c d vcc2 eicedriver sil vcc2 vcc2 gnd2 vee2 vee2 d gcl1 ? (*) c 1 vreg c vr e g iref2 c 1 ref0 c 1 r 1 gn d1 c 1 gn d1 gn d1 gn d1 vee2 d gcl2 ? (*) c d gnd2 gnd2 c d gnd2 c 2 r 2 c 2daclp r daclp vcc1 ocpg c 1 c 1 c 1 r pu2 r pu1 gnd2 c ref1 gnd2 r ref2 c ref2 r osd c osd gnd2 d gcl3 ? (*) r gate (*) r ocpg c acli vee2 d tvsacl2(*)
eicedriver ? sil 1EDI2002AS specification datasheet 130 rev. 3.1, 2015-07-30 hardware description 5.2 absolute maximum ratings stress above the maximum values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 5-2 absolute maximum ratings 1) 1) not subject to production test. absolute maximum ra tings are verified by design / characterization. parameter symbol values unit note / test condition min. typ. max. junction temperature t junc -40 - 150 c storage temperature t sto -55 - 150 c positive power supply (primary) v cc1 -0.3 - 6.0 v referenced to gnd1 positive power supply (secondary) v cc2 -0.3 - 28 v referenced to gnd2 negative power supply v ee2 -13 - 0.3 v referenced to gnd2 power supply voltage difference (secondary) v cc2 -v ee2 v ds2 --40v voltage on any i/o pin on primary side except inp , instp , en/fen v in1 -0.3 - 6.0 v referenced to gnd1 voltage on inp , instp , en/fen pins v inr1 -0.3 - 6.0 v referenced to ref0 voltage difference between ref0 and gnd1 v dg1 -5 - 5 v voltage difference between ocpg and gnd2 v ocpg2 -0.3 - 0.3 v output current on push-pull i/o on primary side i outpp1 --20ma output current on push-pull i/o on secondary side i outpp2 --5ma output current on open drain i/o on primary side i outod1 --20ma output current on pin osd , nuv2 i outod2 --5ma voltage on 5 v pin on secondary side. v in52 -0.3 - 6.5 v referenced to gnd2 voltage on 15 v pin on secondary side. v in152 v ee2 -0.3 - v cc2 +0.3 v referenced to gnd2 , except desat voltage on desat pin. v indesat -0.3 - 20 v referenced to gnd2 esd immunity v esd --2kvhbm 2) 2) according to eia/jesd22-a114-b. --750vcdm 3) , pins 1, 16, 17, 36 3) according to jesd22-c101-c. 500 v cdm 3) , all other pins msl level msl n.a. 3 n.a.
eicedriver ? sil 1EDI2002AS specification datasheet 131 rev. 3.1, 2015-07-30 hardware description 5.3 operating range the following operating conditions must not be exceeded in order to ensure correct operation of the 1EDI2002AS. all parameters specified in the followi ng sections refer to these operating conditions, unless otherwise noticed. 5.4 thermal characteristics the indicated thermal parameters apply to the full operating range, unless otherwise specified. table 5-3 operating conditions parameter symbol values unit note / test condition min. typ. max. ambient temperature t amb -40 - 125 c positive power supply (primary) v cc1 4.65 5.0 5.5 v referenced to gnd1 1) 1) deterministic and correct operation of the device is ensured down to v uvlo1l . positive power supply (secondary) v cc2 13.0 15.0 18.0 v referenced to gnd2 2) 2) deterministic and correct operation of the device is ensured down to v uvlo2l and up to 28v. negative power supply v ee2 -10.0 -8.0 -5.0 v referenced to gnd2 3) 3) deterministic and correct operation of the device is ensured up to 0.3v. pwm switching frequency f sw --30khz 4) 4) maximum junction temperature of the device must not be exceeded. common mode transient immunity dv iso /dt -50 - 50 kv/ sat 500v 5) 5) not subject to production test. this parameter is verified by design / characterization. table 5-4 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance junction to ambient r thja -60-k/wt amb =25c 1) 1) not subject to production test. this parameter is verified by design / characterization. thermal resistance junction to case (bottom) r thjcbot --41k/wt amb =25c 1) ,
eicedriver ? sil 1EDI2002AS specification datasheet 132 rev. 3.1, 2015-07-30 hardware description 5.5 electrical characteristics the indicated electrical parameters apply to the full operating range, unless otherwise specified. 5.5.1 power supply table 5-5 power supplies characteristics parameter symbol values unit note / test condition min. typ. max. uvlo1 threshold high v uvlo1h 4.20 4.45 4.65 v referenced to gnd1 uvlo1 threshold low v uvlo1l 4.15 4.40 4.60 v referenced to gnd1 uvlo1 hysteresis v uvlo1hys 40 70 100 mv uvlo2 threshold high v uvlo2h 11.5 12.5 13.0 v referenced to gnd2 uvlo2 threshold low v uvlo2l 11.0 11.7 12.5 v referenced to gnd2 uvlo2 hysteresis v uvlo2hys 500 850 - mv ovlo2 threshold high v ovlo2h 18.5 19.14 20 v referenced to gnd2 ovlo2 threshold low v ovlo2l 18.5 19.10 20 v referenced to gnd2 uvlo3 threshold high v uvlo3h -12.0 -10.99 -10.0 v referenced to gnd2 uvlo3 threshold low v uvlo3l -12.0 -11.02 -10.0 v referenced to gnd2 ovlo3 threshold high v ovlo3h -5.0 -3.99 -3.0 v referenced to gnd2 ovlo3 threshold low v ovlo3l -5.0 -4.02 -3.0 v referenced to gnd2 v cc2 reset level v rst2 7.9 8.3 8.8 v referenced to gnd2 quiescent current input chip i q1 - 8.0 10.0 ma v cc1 =5.5v, all i/os inactive, opm0 quiescent current output chip (vcc2) i qvcc2 -11.414.0mav cc2 =18v, v ee2 =-10v,all i/os inactive, opm0 quiescent current output chip (vee2) i qvee2 -4.6 -1.1 - ma v cc2 =18, v ee2 =-10v,all i/os inactive, opm0 vcc1 ramp-up / down slew rate |t rp1 | - - 0.5 v/ms absolute value vcc2 ramp-up / down slew rate |t rp2 | - - 1.5 v/ms absolute value vee2 ramp-up / down slew rate |t rp3 | - - 0.8 v/ms absolute value power dissipation - primary chip p dis1 -37-mwt amb =25c, v cc1 = 5v,all i/os inactive, opm0 power dissipation - secondary chip p dis2 -170-mwt amb =25c, v cc2 = 15v, v ee21 = -8v, all i/os inactive, opm0
eicedriver ? sil 1EDI2002AS specification datasheet 133 rev. 3.1, 2015-07-30 hardware description 5.5.2 internal oscillators table 5-6 internal oscillators parameter symbol values unit note / test condition min. typ. max. primary main oscillator frequency f clk1 14.0 16.6 19.1 mhz resistances on pin iref1 nominal secondary main o scillator / start- stop oscillator frequency f clk2 , f clkst2 15.0 17.1 19.0 mhz resistances on pin iref2 nominal
eicedriver ? sil 1EDI2002AS specification datasheet 134 rev. 3.1, 2015-07-30 hardware description 5.5.3 primary i/o electr ical characteristics table 5-7 electrical characteristics for pins: inp , instp , en/fen parameter symbol values unit note / test condition min. typ. max. low input voltage v inprl1 0 - 0.3xv cc1 v referenced to ref0 high input voltage v inprh1 0.7xv cc1 -v cc1 v referenced to ref0 weak pull down resistance inp , instp , en/fen r pdin1 20 - 100 k to ref0 input current |i inpr1 |--300 a input pulse suppression t inps1 -20-ns 1) 1) not subject to production test. this parameter is verified by design / characterization. time between en/fen valid and inp high level t inpen 8--ssee chapter 2.4.3 inp high / low duration t inppd 250--ns 1) instp high / low duration t instppd 250--ns 1) duration between en/fen valid-to- invalid transition a nd the next invalid- to-valid transition t eninv 8--s 1) table 5-8 electrical characteristics for pins: nrst/rdy , sclk , sdi , ncs , dio1 (input) parameter symbol values unit note / test condition min. typ. max. low input voltage v inpl1 0 - 0.3xv cc1 v referenced to gnd1 high input voltage v inph1 0.7xv cc1 -v cc1 v referenced to gnd1 weak pull up resistance to sclk , sdi , ncs r puspi1 26.5 - 100 k to vcc1 . weak pull down resistance on dio1 r pddio1 26.5 - 100 k to gnd1 , input current |i inp1 |--400 a nrst/rdy output voltage in non- ready conditions. v outnr --1vv cc1 =5v, i load = 2 ma -0.71vv cc1 =0v, i load = 500 a nrst/rdy driven-active time after power supplies are within operating range. t rst -15.4-s 1) 1) not subject to production test. this parameter is verified by design / characterization. nrst/rdy minimum activation time. t rstat 10--s
eicedriver ? sil 1EDI2002AS specification datasheet 135 rev. 3.1, 2015-07-30 hardware description table 5-9 electrical characteristics for pins: sdo , dout , dio1 (output) parameter symbol values unit note / test condition min. typ. max. low output voltage v outpl1 --0.5vi load = 5ma high output voltage v outph1 3.85 - - v i load = 5ma table 5-10 electrical characteristics for pins: nflta , nfltb parameter symbol values unit note / test condition min. typ. max. low output voltage v outdl1 --0.5vi sink =5ma
eicedriver ? sil 1EDI2002AS specification datasheet 136 rev. 3.1, 2015-07-30 hardware description 5.5.4 secondary i/o electrical characteristics table 5-11 electrical characteristics for pins: gate , desat parameter symbol values unit note / test condition min. typ. max. desat input voltage range v 15desat 0- v cc2 v referenced to gnd2 1) 2) 1) pin is robust against negative transient 2) not subject to production test. this parameter is verified by design / characterization. gate input voltage range v 15gate v ee2 -v cc2 v referenced to gnd2 2) gate passive clamp ing voltage v pclpg --v ee2 +1 v secondary chip not supplied, i clamp =10 ma. gate passive clamp current i pclpg 5 - - ma secondary chip not supplied, v gate =v ee2 +2v table 5-12 electrical characteristics for pins: ton , toff parameter symbol values unit note / test condition min. typ. max. output voltage high v 15oh2 v cc2 -1 - v cc2 +0.3 v referenced to gnd2 output voltage low v 15ol2 v ee2 -0.3 - v ee2 +1 v referenced to gnd2 source / sink current i 15o2 1--apin toff / ton 1) 1) not subject to production test. this parameter is verified by design / characterization. passive clamping voltage v pclp --v ee2 +2 v secondary chip not supplied, i clamp =10 ma. table 5-13 electrical characteristics for pins: osd , debug , dio2 (input) parameter symbol values unit note / test condition min. typ. max. low input voltage v 5inl2 0 - 1.5 v referenced to gnd2 high input voltage v 5inh2 3.5 - 5.5 v referenced to gnd2 weak pull down on dio2 r pddio2 40 100 175 k to gnd2 . weak pull down on debug r pdin2 40 100 175 k to gnd2 . weak pull down on osd r pdosd2 60 100 175 k to gnd2
eicedriver ? sil 1EDI2002AS specification datasheet 137 rev. 3.1, 2015-07-30 hardware description table 5-14 electrical characteristics for pin: nuv2 parameter symbol values unit note / test condition min. typ. max. low output voltage v outdl2 0- 0.5vi sink =5ma, referenced to gnd2 table 5-15 electrical characteristics for pins: daclp , dio2 (output) parameter symbol values unit note / test condition min. typ. max. output voltage high v 5oh2 4.0 - 5.25 v referenced to gnd2 ,i load = 2ma output voltage low v 5ol2 0 - 0.5 v referenced to gnd2 ,i load = 2ma table 5-16 electrical characteristics for pin: vreg parameter symbol values unit note / test condition min. typ. max. vreg output voltage range v reg2 4.75 5 5.30 v referenced to gnd2 , c load =1f vreg output dc current i reg2 --525a 1) 1) not subject to production test. this parameter is verified by design / characterization.
eicedriver ? sil 1EDI2002AS specification datasheet 138 rev. 3.1, 2015-07-30 hardware description 5.5.5 switching characteristics table 5-17 switching characteristics parameter symbol values unit note / test condition min. typ. max. input to output propagation delay on t pdon 175 215 255 ns v cc1 =5v, v cc2 =15v, v ee2 =-8v input to output propagation delay off t pdoff 175 215 255 ns v cc1 =5v, v cc2 =15v, v ee2 =-8v input to output propagation delay distortion (t pdoff -t pdon ) t pdisto -20 0 40 ns v cc1 =5v, v cc2 =15v, v ee2 =-8v input to output propagation delay distortion variation for two consecutive pulses t pdistov -25-nsv cc1 =5v, v cc2 =15v, v ee2 =-8v, t junc =25c 1) rise time t rise -120205nsv cc1 =5v, v cc2 =15v, v ee2 =-8v, c load = 10nf, 10%-90% - 3050nsv cc1 =5v, v cc2 =15v, v ee2 =-8v, no load, 90%- 10% fall time t fall -150235nsv cc1 =5v, v cc2 =15v, v ee2 =-8v, c load = 10nf, 90%-10% -60100nsv cc1 =5v, v cc2 =15v, v ee2 =-8v, no load, 90%- 10% ttoff plateau level v gpof0 9.250 9.740 10.250 v referenced to gnd2 , measured at pin ton (shorted with toff ) vcc2=15v,t junc =25c, no vbe compensation. v gpof1 9.335 9.820 10.335 v ... ... ... ... ... v gpof14 10.440 10.95 11.440 v v gpof15 11.1 11.7 12.3 v ttoff plateau level v gpof0 8.600 9.08 9.600 v referenced to gnd2 , measured at pin ton (shorted with toff ) vcc2=15v,t junc =25c, with vbe compensation. v gpof1 8.685 9.16 9.685 v ... ... ... ... ... v gpof14 9.790 10.28 10.790 v v gpof15 10.4 11.0 11.6 v variation from configured v ttoff @ t j = - 40c dv tm40 -40-mv 1) variation from configured v ttoff @ t j = 150c dv t150 --80-mv 1) ttoff decrease rate t slew -9-v/ s ttoff delay deviation from nominal value t devttoff -100 0 100 ns for a target time of 2s, using the tcf. 1)
eicedriver ? sil 1EDI2002AS specification datasheet 139 rev. 3.1, 2015-07-30 hardware description ttoff (regular) plateau time t ttoff 2.00 2.22 2.54 s srttof . rtval =26 h , assuming no tcf. gate voltage reference 1 v gate1 -v ee2 +2 - v measured at pin gate gate voltage reference 2 v gate2 -v cc2 -3 - v measured at pin gate output stage monitoring ( ton ) v osmon -v cc2 -3 - v output stage monitoring ( toff ) v osmof -v ee2 +2 - v active clamping activation time t acl 2.00 2.22 2.54 s default value of bit field saclt . at . wto & tton plateau level v gpon0 8.65 9.25 9.95 v referenced to gnd2 , measured at pin ton (shorted with toff ) vcc2=15v,t junc =25c, no vbe compensation. v gpon1 9.85 10.5 11.25 v v gpon2 10.75 11.4 12.1 v wto & tton plateau level v gpon0 9.15 9.9 10.75 v referenced to gnd2 , measured at pin ton (shorted with toff ) vcc2=15v,t junc =25c, with vbe compensation. v gpon1 10.4 11.0 11.6 v v gpon2 11.1 11.6 12.2 v tton delay t tton 0.78 0.88 1.00 s scfg2 . ttond =f h , assuming no tcf. 1) not subject to production test. parameters are verified by design / characterization. table 5-17 switching characteristics (cont?d) parameter symbol values unit note / test condition min. typ. max.
eicedriver ? sil 1EDI2002AS specification datasheet 140 rev. 3.1, 2015-07-30 hardware description 5.5.6 desaturation protection 5.5.7 overcurrent protection table 5-18 desat characteristics parameter symbol values unit note / test condition min. typ. max. desat reference level v desat0 8.4 9 9.4 v v cc2 =15v, v ee2 =-8v v desat1 9.25 10 10.45 v v desat2 7.4 8 8.4 v v desat3 6.5 7 7.5 v desat pull-up resistance r pudsat2 19.5 30 50 k to vcc2 desat low voltage v desatl -200-mv referenced to gnd2 , desat clamping enabled, i sink = 5ma. desat blanking time deviation from programmed value dt desatbl -20 - +20 % after transition of the pwm command, assuming a 1 s programmed blanking time 1) 1) not subject to production test. parameters are verified by design / characterization. table 5-19 ocp characteristics parameter symbol values unit note / test condition min. typ. max. oc error detection threshold v ocpd1 270 300 330 mv referenced to ocpg oc current warning detection threshold v ocpd2 35 50 70 mv referenced to ocpg ocp blanking time deviation from programmed value dt ocpbl -20 - +20 % after transition of the pwm command, assuming a 1 s programmed blanking time 1) 1) not subject to production test. parameters are verified by design / characterization. ocp pull-up resistance r puocp2 40 100 175 k to internal 5v reference.
eicedriver ? sil 1EDI2002AS specification datasheet 141 rev. 3.1, 2015-07-30 hardware description 5.5.8 low latency digital channel 5.5.9 dout table 5-20 digital channel characteristics parameter symbol values unit note / test condition min. typ. max. input to output propagation time on (secondary to primary) t dspon -2.04.5s pcfg2 . dio1 =1 b , scfg2 . dio2 =0 b input to output propagation time off (secondary to primary) t dspoff -2.04.5s input to output propagation time on (primary to secondary) t dpson -2.04.5s pcfg2 . dio1 =0 b , scfg2 . dio2 =1 b input to output propagation time off (primary to secondary) t dpsoff -2.04.5s table 5-21 data out characteristics parameter symbol values unit note / test condition min. typ. max. desat comparator output transition to dout transition. t spdout -2.04.5s
eicedriver ? sil 1EDI2002AS specification datasheet 142 rev. 3.1, 2015-07-30 hardware description 5.5.10 over temperature warning table 5-22 over temperature warning characteristics parameter symbol values unit note / test condition min. typ. max. threshold junction temperature t j_ovt 140 - - c 1) 1) not subject to back-end test
eicedriver ? sil 1EDI2002AS specification datasheet 143 rev. 3.1, 2015-07-30 hardware description 5.5.11 error detection timing table 5-23 error detection timing parameter symbol values unit note / test condition min. typ. max. dead time for shoot through protection t dead 840 - 1200 ns default value of bit field pcfg2 . stpdel class a event detection to nflta activation t aflta -24.5 s class a event detection to turn off sequence activation t offcla --400nsv toff =v cc2 - 1 v desat event detection to turn off sequence activation t offdesat2 --430nsv toff =v cc2 - 1 v, after blanking time elapsed ocp event occurrence to turn off sequence activation t offocp2 - 110 130 ns v toff =v cc2 - 1 v, after blanking time elapsed class b event detection to nfltb activation t bfltb -24.5 s class b event detection to turn off sequence activation t offclb2 --400nsv toff =v cc2 - 1 v 1) 1) verified by design / characterization. not tested in production. verification mode time out t vmto - 15 - ms after a transition from opm2 to opm5, scfg . tosen = 0 b - 60 - ms after a transition from opm2 to opm5, scfg . tosen = 1 b gate monitoring time out t gmto -15.0-s 1) life sign error detection time t ls - 5 - s after error condition detected by logic. output stage monitor inhibit time. t osm - 4 - s after hard transition 1) . en/fen half-pulse acceptance window t fenw 1.20 3.00 s pcfg2 . fen =1 b , f osc1 =16.6mhz 1)
eicedriver ? sil 1EDI2002AS specification datasheet 144 rev. 3.1, 2015-07-30 hardware description 5.5.12 spi interface figure 5-2 spi interface timing table 5-24 spi interface characteristics parameter symbol values unit note / test condition min. typ. max. spi frame size n bit n.a. n*16 n.a. bit n is the daisy chain length baud rate f sclk 0.1 - 2.0 mhz standard spi configuration, 1) 1) low limit verified by design / characterization. not tested in production. 0.1 - 1.8 mhz daisy chain configuration, 1) sclk duty cycle d sclk 45 - 55 % 2) 2) verified by design / characterization. not tested in production. sdi set-up time t sdisu 65--ns 2) sdi hold time t sdih 100--ns 2) ncs lead time t cslead 1- - s 2) ncs trail time t cstrail 1- - s 2) ncs inactive time t csinact 10 - - s 2) sdo enable time t sdoen --500nsc load =20pf 2) sdo disable time t sdodis --1 sc load =20pf 2) sdo valid time t sdov 10 - 185 ns c load =20pf 2) ncs sclk sdo sdi t sdoen t sdodis t cslead t cstrail t csinact t sclkhigh t sclklow t sdisu t sdih t sclkp t sdov
eicedriver ? sil 1EDI2002AS specification datasheet 145 rev. 3.1, 2015-07-30 hardware description 5.5.13 insulation characteristics table 5-25 isolation characteristics referring to din en 60747-5-2 (vde 0884 - 2):2003-01 description symbol characteristic unit installation classification per en60664-1, table 1: rated main voltage less than 150 v rms rated main voltage less than 300 v rms rated main voltage less than 600 v rms i - iv i - iii i - ii climatic classification 40 / 125 / 21 pollution degree (en 60664-1) 2 minimum external clearance clr 8.12 mm minimum external creepage cpg 8.24 mm minimum comparative tracking index cti 175 maximum repetitive insulation voltage v iorm 1420 v peak highest allowable overvoltage 1) 1) refer to vde 0884 for a detailed description of method a and method b partial discharge v iotm 6000 v peak maximum surge insulation voltage v iosm 6000 v peak table 5-26 isolation characteristics referring to ul 1577 description symbol characteristic unit insulation test voltage / 1 min v iso 3750 v rms insulation test voltage / 1 sec v iso 4500 v rms
eicedriver ? sil 1EDI2002AS package information datasheet 146 rev. 3.1, 2015-07-30 hardware description 6 package information figure 6-1 package dimensions figure 6-2 recommended footprint
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